SAM3N00A Atmel Corporation, SAM3N00A Datasheet - Page 391

• Manufacturer Part Number: SAM3N00A
• Manufacturer: Atmel Corporation

26.5.7
Figure 26-4. Output Line Timings
26.5.8
26.5.9
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
Write PIO_ODSR at 1
Write PIO_ODSR at 0
Write PIO_CODR
Write PIO_SODR
Output Line Timings
Inputs
Input Glitch and Debouncing Filters
PIO_ODSR
PIO_PDSR
MCK
The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and
PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O line
is controlled by the PIO controller or assigned to a peripheral function. PIO_MDSR (Multi-driver
Status Register) indicates the pins that are configured to support external drivers.
After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0.
Figure 26-4
directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is
set.
The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This reg-
ister indicates the level of the I/O lines regardless of their configuration, whether uniquely as an
input or driven by the PIO controller or driven by a peripheral.
Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise
PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
Optional input glitch and debouncing filters are independently programmable on each I/O line.
The glitch filter can filter a glitch with a duration of less than 1/2 Master Clock (MCK) and the
debouncing filter can filter a pulse of less than 1/2 Period of a Programmable Divided Slow
Clock.
The selection between glitch filtering or debounce filtering is done by writing in the registers
PIO_IFSCDR (PIO Input Filter Slow Clock Disable Register) and PIO_IFSCER (PIO Input Filter
Slow Clock Enable Register). Writing PIO_IFSCDR and PIO_IFSCER respectively, sets and
clears bits in PIO_IFSCSR.
The current selection status can be checked by reading the register PIO_IFSCSR (Input Filter
Slow Clock Status Register).
• If PIO_IFSCSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 Period
of Master Clock.
Figure 26-4
APB Access
shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by
also shows when the feedback in PIO_PDSR is available.
2 cycles
APB Access
2 cycles
SAM3N
SAM3N
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