SAM3N00A Atmel Corporation, SAM3N00A Datasheet - Page 340

• Manufacturer Part Number: SAM3N00A
• Manufacturer: Atmel Corporation

23.6
23.6.1
340
Divider and PLL Block
SAM3N
Divider and Phase Lock Loop Programming
The device features a Divider/PLL Block that permits a wide range of frequencies to be selected
on either the master clock, the processor clock or the programmable clock outputs.
Figure 23-4
Figure 23-4. Divider and PLL Block Diagram
The divider can be set between 1 and 255 in steps of 1. When the divider field (DIV) is set to 0,
the output of the divider and the PLL output is a continuous signal at level 0. On reset, the DIV
field is set to 0, thus the PLL input clock is set to 0.
The PLL allows multiplication of the divider’s output. The PLL clock signal has a frequency that
depends on the respective source signal frequency and on the DIV and MUL parameters. The
factor applied to the source signal frequency is (MUL + 1)/DIV. When MUL is written to 0, the
PLL is disabled and its power consumption is saved. Re-enabling the PLL can be performed by
writing a value higher than 0 in the MUL field.
Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK bit in PMC_SR
is automatically cleared. The value written in the PLLCOUNT field in CKGR_PLLR is loaded in
the PLL counter. The PLL counter then decrements at the speed of the Slow Clock until it
reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the pro-
cessor. The user has to load the number of Slow Clock cycles required to cover the PLL
transient time into the PLLCOUNT field.
The PLL clock can be divided by 2 by writing the PLLDIV2 bit in PMC_MCKR register.
It is forbidden to change 4/8/12 Fast RC oscillator frequency or main selection in CKGR_MOR
register while Master clock source is PLL and PLL reference clock is Fast RC oscillator.
The user must:
• Switch on the Main RC oscillator by writing 1 in CSS field of PMC_MCKR.
• Change the frequency (MOSCRCF) or oscillator selection (MOSCSEL) in CKGR_MOR.
• Wait for MOSCRCS (if frequency changes) or MOSCSELS (if oscillator selection changes) in
• Disable and then enable the PLL (LOCK in PMC_IDR and PMC_IER register)
• Wait for PLLRDY.
• Switch back to PLL.
PMC_IER.
shows the block diagram of the divider and PLL block.
MAINCK
SLCK
Divider
DIV
PLLCOUNT
Counter
PLL
MUL
PLL
OUT
LOCK
PLLCK
11011A–ATARM–04-Oct-10