SAM3N00A Atmel Corporation, SAM3N00A Datasheet - Page 98

• Manufacturer Part Number: SAM3N00A
• Manufacturer: Atmel Corporation

10.12.6.3
10.12.6.4
10.12.6.5
10.12.6.6
98
LDM
STMDB
STM
LDM
SAM3N
Restrictions
Condition flags
Examples
Incorrect examples
R8,{R0,R2,R9}
R1!,{R3-R6,R11,R12}
R5!,{R5,R4,R9} ; Value stored for R5 is unpredictable
R2, {}
The accesses happen in order of decreasing register numbers, with the highest numbered regis-
ter using the highest memory address and the lowest number register using the lowest memory
address. If the writeback suffix is specified, the value of Rn - 4 * (n-1) is written back to Rn.
The PUSH and POP instructions can be expressed in this form. See
99
In these instructions:
When PC is in reglist in an LDM instruction:
These instructions do not change the flags.
• Rn must not be PC
• reglist must not contain SP
• in any STM instruction, reglist must not contain PC
• in any LDM instruction, reglist must not contain PC if it contains LR
• reglist must not contain Rn if you specify the writeback suffix.
• bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to
• if the instruction is conditional, it must be the last instruction in the IT block.
for details.
this halfword-aligned address
; There must be at least one register in the list
; LDMIA is a synonym for LDM
“PUSH and POP” on page
11011A–ATARM–04-Oct-10