SAM3N00A Atmel Corporation, SAM3N00A Datasheet - Page 477

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SAM3N00A

Manufacturer Part Number
SAM3N00A
Description
Manufacturer
Atmel Corporation
Datasheets
Figure 28-18. TWI Read Operation with Single Data Byte without Internal Address
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
Read Receive Holding Register
Set the Master Mode register:
TWI_CR = MSEN + SVDIS
TWI_CR = START | STOP
Read ==> bit MREAD = 1
Set the Control register:
- Device slave address
- Transfer direction bit
Read Status register
Read status register
(Needed only once)
Start the transfer
- Master enable
Yes
TXCOMP = 1?
Yes
Set TWI clock
RXRDY = 1?
BEGIN
END
No
No
SAM3N
SAM3N
477
477

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