SAM3N00A Atmel Corporation, SAM3N00A Datasheet - Page 644

• Manufacturer Part Number: SAM3N00A
• Manufacturer: Atmel Corporation

32.7.9
Name:
Addresses:
Access:
• CPRE: Channel Pre-scaler
Values which are not listed in the table must be considered as “reserved”.
• CALG: Channel Alignment
0 = The period is left aligned.
1 = The period is center aligned.
• CPOL: Channel Polarity
0 = The output waveform starts at a low level.
1 = The output waveform starts at a high level.
• CPD: Channel Update Period
0 = Writing to the PWM_CUPDx will modify the duty cycle at the next period start event.
1 = Writing to the PWM_CUPDx will modify the period at the next period start event.
644
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
31
23
15
–
–
–
7
–
SAM3N
PWM Channel Mode Register
MCK
MCKDIV2
MCKDIV4
MCKDIV8
MCKDIV16
MCKDIV32
MCKDIV64
MCKDIV128
MCKDIV256
MCKDIV512
MCKDIV1024
CLKA
CLKB
Name
30
22
14
0x40020200 [0], 0x40020220 [1], 0x40020240 [2], 0x40020260 [3]
–
–
–
6
–
PWM_CMR[0..3]
Read/Write
Master Clock
Master Clock divided by 2
Master Clock divided by 4
Master Clock divided by 8
Master Clock divided by 16
Master Clock divided by 32
Master Clock divided by 64
Master Clock divided by 128
Master Clock divided by 256
Master Clock divided by 512
Master Clock divided by 1024
Clock A
Clock B
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
Description
27
19
11
–
–
–
3
CPD
26
18
10
–
–
2
CPRE
CPOL
25
17
–
–
9
1
11011A–ATARM–04-Oct-10
CALG
24
16
–
–
8
0