AD9434 Analog Devices, AD9434 Datasheet - Page 22

• Manufacturer Part Number: AD9434
• Description: 12-Bit, 370 MSPS/500 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9434

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 500MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: 1.5 V p-p,Bip 0.75V
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9434
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 12.
If it is desired to change the output data format to twos comple-
ment, see the AD9434 Configuration Using the SPI section.
An output clock signal is provided to assist in capturing data
from the AD9434. The DCO is used to clock the output data
and is equal to the sampling clock (CLK) rate. In single data
rate mode (SDR), data is clocked out of the AD9434 and must
be captured on the rising edge of the DCO. In double data rate
mode (DDR), data is clocked out of the AD9434 and must be
captured on the rising and falling edges of the DCO. See the
timing diagrams shown in Figure 2 and Figure 3 for more
information.
Output Data Rate and Pinout Configuration
The output data of the AD9434 can be configured to drive 12
pairs of LVDS outputs at the same rate as the input clock signal
(SDR mode), or six pairs of LVDS outputs at 2× the rate of the
input clock signal (DDR mode). SDR is the default mode; the
device can be reconfigured for DDR by setting Bit 3 in Register 14
(see Table 13).
Figure 49. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less
Figure 50. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths
–100
–200
–300
–400
–500
–200
–400
–600
500
400
300
200
100
600
400
200
0
0
–3
–3
Greater than 24 Inches on Standard FR-4, AD9434-500
–2
–2
than 24 Inches on Standard FR-4, AD9434-500
–1
–1
TIME (ns)
TIME (ns)
0
0
1
1
2
2
3
3
14
12
10
12
10
–100
8
6
4
2
0
8
6
4
2
0
–40
–20
TIME (ps)
TIME (ps)
0
0
20
10
40
0
Rev. A | Page 22 of 28
Out-of-Range (OR)
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OR+ and OR− (OR±)
are digital outputs that are updated along with the data output
corresponding to the particular sampled input voltage. Thus,
OR± has the same pipeline latency as the digital data. OR± is
low when the analog input voltage is within the analog input
range and high when the analog input voltage exceeds the input
range, as shown in Figure 51. OR± remains high until the analog
input returns to within the input range and another conversion
is completed. By logically AND’ing OR± with the MSB and its
complement, overrange high or underrange low conditions can
be detected.
TIMING
The AD9434 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propaga-
tion delay (t
Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD9434. These transi-
ents can degrade the dynamic performance of the converter.
The AD9434 also provides a data clock output (DCO) intended
for capturing the data in an external register. The data outputs are
valid on the rising edge of DCO.
The lowest conversion rate of the AD9434 is 50 MSPS. At clock
rates below 1 MSPS, the AD9434 assumes the standby mode.
VREF
The AD9434 VREF pin (Pin 31) allows the user to monitor the
on-board voltage reference, or provide an external reference
(requires configuration through the SPI). The three optional
settings are internal V
export V
to this pin. VREF is internally compensated and additional
loading may impact performance.
AD9434 CONFIGURATION USING THE SPI
The AD9434 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space inside the ADC. This gives the user added flexibility to
customize device operation depending on the application.
Addresses are accessed (programmed or readback) serially in
1-byte words. Each byte can be further divided into fields,
which are documented in the Memory Map section.
OR± DATA OUTPUTS
1
0
0
0
0
1
Figure 51. OR± Relation to Input Voltage and Output Data
REF
1111
1111
1111
0000
0000
0000
, and import V
PD
1111
1111
1111
0000
0000
0000
) after the rising edge of the clock signal.
1111
1111
1110
0001
0000
0000
REF
–FS – 1/2 LSB
(pin is connected to 20 kΩ to ground),
OR±
REF
. Do not attach a bypass capacitor
–FS
–FS + 1/2 LSB
+FS – 1/2 LSB
+FS – 1 LSB
+FS