AD9434 Analog Devices, AD9434 Datasheet - Page 24

• Manufacturer Part Number: AD9434
• Description: 12-Bit, 370 MSPS/500 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9434

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 500MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: 1.5 V p-p,Bip 0.75V
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9434
Table 11. Serial Timing Definitions
Parameter
t
t
t
t
t
t
t
t
t
Table 12. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
SCLK DON’T CARE
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
SDIO DON’T CARE
CSB
Min (ns)
5
2
40
5
2
16
16
1
5
Condition (V)
< −0.75 − 0.5 LSB
= −0.75
= 0
= 0.75
> 0.75 + 0.5 LSB
t
S
R/W
t
DS
W1
W0
t
DH
t
HIGH
A12
Offset Binary Output Mode, D11 to D0
0000 0000 0000
0000 0000 0000
1000 0000 0000
1111 1111 1111
1111 1111 1111
Description
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 52)
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising
edge (not shown in Figure 52)
A11
Figure 52. Serial Port Interface Timing Diagram
A10
t
LOW
A9
Rev. A | Page 24 of 28
t
CLK
A8
A7
D5
Twos Complement Mode, D11 to D0
1000 0000 0000
1000 0000 0000
0000 0000 0000
0111 1111 1111
0111 1111 1111
D4
D3
D2
D1
D0
t
H
DON’T CARE
DON’T CARE
OR±
1
0
0
0
1