AD9434 Analog Devices, AD9434 Datasheet - Page 25

• Manufacturer Part Number: AD9434
• Description: 12-Bit, 370 MSPS/500 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9434

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 500MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: 1.5 V p-p,Bip 0.75V
• Adc Architecture: Pipelined
• Pkg Type: CSP

MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map table (see Table 13) has eight
address locations. The memory map is roughly divided into
three sections: chip configuration register map (Address 0x00 to
Address 0x02), transfer register map (Address 0xFF), and ADC
functions register map (Address 0x08 to Address 0x2A).
The Addr. (Hex) column of the memory map indicates the
register address in hexadecimal, and the Default Value (Hex)
column shows the default hexadecimal value that is already
written into the register. The Bit 7 (MSB) column is the start of
the default hexadecimal value given. For example, Hexadecimal
Address 0x2A, OVR_CONFIG, has a hexadecimal default value
of 0x01. This means that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0,
Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in
binary. The default value enables the OR± output. Overwriting
this default so that Bit 0 = 0 disables the OR± output. For more
information on this and other functions, consult the
Application Note, Interfacing to High-Speed ADCs via SPI® at
www.analog.com.
Table 13. Memory Map Register
Addr.
(Hex)
Chip Configuration Registers
00
01
02
Transfer Register
FF
ADC Functions Registers
08
DEVICE_UPDATE
Register Name
CHIP_PORT_CONFIG
CHIP_ID
CHIP_GRADE
Modes
0
0
Bit 7
(MSB)
0
0
Bit 6
LSB
first
0
0
0
Bit 5
Soft
reset
0
PDWN:
0 = full
(default)
1 =
standby
0
AN-877
8-bit chip ID, Bits[7:0] = 0x6A
Rev. A | Page 25 of 28
Bit 4
1
0
0
00 = 500 MSPS
01 = 370 MSPS
Speed grade:
Bit 3
1
0
0
RESERVED LOCATIONS
Undefined memory locations should not be written to other
than with the default values suggested in this data sheet. Addresses
that have values marked as 0 should be considered reserved and
have a 0 written into their registers during power-up.
DEFAULT VALUES
Exiting out of reset, critical registers are preloaded with default
values. These values are indicated in Table 13. Other registers
do not have default values and retain the previous value when
exiting reset.
LOGIC LEVELS
An explanation of various registers follows: “Bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit. ” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit. ”
Bit 2
Soft
reset
X
0
1
Note that external PDWN pin
Internal power-down mode:
011 = normal (power-up)
000 = normal (power-up,
001 = full power-down
overrides this setting
010 = standby
Bit 1
LSB
first
X
0
default)
1
X
Bit 0
(LSB)
0
X
SW
transfer
1
Default
Value
(Hex)
0x18
Read
only
Read
only
0x00
0x00
Default Notes/
Comments
The nibbles
should be
mirrored by the
user so that LSB
or MSB first
mode registers
correctly,
regardless of
shift mode.
Default is a
unique chip ID,
different for
each device.
This is a read-
only register.
Child ID used to
differentiate
graded devices.
Synchronously
transfers data
from the master
shift register to
the slave.
Determines
various generic
modes of chip
operation.
AD9434