AD9963

Manufacturer Part NumberAD9963
Description10-/12-Bit, Low Power, Broadband MxFE
ManufacturerAnalog Devices
AD9963 datasheet
 


Specifications of AD9963

Resolution (bits)12bitThroughput Rate100MSPS
# Chan2Supply VMulti(+1.8Anlg, +1.8Dig),Multi(+1.8Anlg, +3.3Dig) ,Single(+1.8),Single(+3.3)
Sample Rate100MSPSAdc Bits X #adcs-speed12x2-100 MHz
Dac Bits X #dacs-clkspeed12x2-170 MHzPkg TypeCSP
Primary ApplicationBroadband Wireless  
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FEATURES
Dual 10-bit/12-bit, 100 MSPS ADC
SNR = 67 dB, f
= 30.1 MHz
IN
Dual 10-bit/12-bit, 170 MSPS DAC
ACLR = 74 dBc
5 channels of analog auxiliary input/output
Low power, <425 mW at maximum sample rates
Supports full and half-duplex data interfaces
Small 72-lead LFCSP lead-free package
APPLICATIONS
Wireless infrastructure
Picocell, femtocell basestations
Medical instrumentation
Ultrasound AFE
Portable instrumentation
Signal generators, signal analyzers
GENERAL DESCRIPTION
The AD9961/AD9963 are pin-compatible, 10-/12-bit, low
power MxFE® converters that provide two ADC channels with
sample rates of 100 MSPS and two DAC channels with sample
rates to 170 MSPS. These converters are optimized for transmit
and receive signal paths of communication systems requiring low
power and low cost. The digital interfaces provide flexible
clocking options. The transmit is configurable for 1×, 2×, 4×,
and 8× interpolation. The receive path has a bypassable 2×
decimating low-pass filter.
The AD9961 and AD9963 have five auxiliary analog channels.
Three are inputs to a 12-bit ADC. Two of these inputs can be
configured as outputs by enabling 10-bit DACs. The other
two channels are dedicated outputs from two independent
12-bit DACs.
The high level of integrated functionality, small size, and low
power dissipation of the AD9961/AD9963 make them well-
suited for portable and low power applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Low Power, Broadband MxFE
AD9961/AD9963
FUNCTIONAL BLOCK DIAGRAM
AD9961/AD9963
TEMPERATURE
SENSOR
AUX
ADC
DLLFILT
DLL AND
AUX
CLOCK
DAC
CLKP
DISTRIBUTION
AUX
CLKN
DAC
INTERNAL
TXCLK
TXIQ/TXnRX
LPF
1/2/4/8
TXD[11:0]
DATA
LPF
ASSEMBLER
1/2/4/8
TRXCLK
TRXIQ
LPF
1/2
TRXD[11:0]
LPF
1/2
RESET
SERIAL
SDIO
PORT
SCLK
LOGIC
CS
REFERENCES
AND BIAS
Figure 1.
PRODUCT HIGHLIGHTS
1.
High Performance with Low Power Consumption.
The DACs operate on a single 1.8 V to 3.3 V supply.
Transmit path power consumption is <100 mW at 170
MSPS. Receive path power consumption is <350 mW at
100 MSPS from 1.8 V supply. Sleep and power-down
modes are provided for low power idle periods.
2.
High Integration.
The dual transmit and dual receive data converters, five
channels of auxiliary data conversion and clock generation
offer complete solutions for many modem designs.
3.
Flexible Digital Interface.
The interface mates seamlessly to most digital baseband
processors.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
10-/12-Bit,
AUXIN1
MUX
AUXIO2
AUXIO3
TXIP
12-BIT
DAC
TXIN
TXQP
12-BIT
DAC
TXQN
RXIP
12-BIT
ADC
RXIN
RXQP
12-BIT
ADC
RXQN
AUX
DAC12A
DAC
AUX
DAC12B
DAC
LDO
VREGs
www.analog.com

AD9963 Summary of contents

  • Page 1

    ... The transmit is configurable for 1×, 2×, 4×, and 8× interpolation. The receive path has a bypassable 2× decimating low-pass filter. The AD9961 and AD9963 have five auxiliary analog channels. Three are inputs to a 12-bit ADC. Two of these inputs can be configured as outputs by enabling 10-bit DACs. The other two channels are dedicated outputs from two independent 12-bit DACs ...

  • Page 2

    ... AD9961/AD9963 TABLE OF CONTENTS Features .............................................................................................. 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8 Pin Configurations and Function Descriptions ........................... 9 Typical Performance Characteristics ........................................... 13 Terminology .................................................................................... 18 Theory of Operation ...................................................................... 19 Serial Control Port .......................................................................... 20 General Operation of Serial Control Port ............................... 20 Sub Serial Interface Communications ..................................... 21 Configuration Registers ...

  • Page 3

    ... REFIO 0.8 175 175 −140 −136 70 21.875 21.875 43.75 43.75 87.5 87.5 175 175 Rev Page AD9961/AD9963 AD9963 Typ Max Unit 12 Bits 0.3 LSB 0.4 +10 %FSR 0.4 +2.4 %FSR +0.03 %FSR 2.0 mA +1.0 V +1 ppm/°C ±40 ppm/°C 1. kΩ ±25 ppm/°C 1.2 V REFIO ...

  • Page 4

    ... OUT DAC DATA Stop-Band Rejection (f ± 0.4 × f DATA DATA AD9961 Min Typ 10 0.1 ±1 ±0.5 1.56 8 100 1 Rev Page AD9963 Max Min Typ Max 12 0.3 ±1 ±0.5 1.56 8 100 1.4 0.1 0.1 49 0.2 70 Unit Bits LSB %FSR %FSR V p-p diff pF ...

  • Page 5

    ... Maximum Sample Rate AD9961 Min Typ Max Min 12 12 ±0.8 ±2 ±1.0 ±2 −1.0 +1.0 −1.0 −2.0 +2.0 −2 Rev Page AD9961/AD9963 AD9963 Typ Max Units Bits ±0.8 LSB ±2 µs Bits ±1.0 LSB ±2 µs Bits +1.0 LSB +2.0 % 3.2 V kHz ...

  • Page 6

    ... CLK33V, TXVDD (These Supplies Must Be Tied Together) DRVDD DVDD18V CLK18V DLL18V RX18V RX18VF RX33V AUX33V (AUXADC Enabled) AUX33V (AUXADC Disabled) AD9961 Min Typ Max 1.65 10.7 29.4 21.0 3.84 9.98 79.2 34.3 12.1 17.0 113 93 0.55 1.72 3.63 1.72 3.63 1.72 1.89 1.72 1.89 1.72 1.89 1.72 1.89 1.72 1.89 2.50 3.63 3.14 3.63 1.72 3.63 Rev Page AD9963 Min Typ Max Unit 1.65 mA 10.7 mA 34.9 mA 22.7 mA 3.84 mA 9.98 mA 79.2 mA 34.3 mA 12.1 mA 17.0 mA 113 mA 108 mA 0.55 mA 1.72 3.63 V 1.72 3.63 V 1.72 1.89 V 1.72 1.89 V 1.72 1.89 V 1.72 1. ...

  • Page 7

    ... Data Valid, SDIO (Data Out) to SCLK (t DV Setup Time SCLK ( Conditions DRVDD = 1.8 V DRVDD = 2.5 V DRVDD = 3.3 V DRVDD = 1.8 V DRVDD = 2.5 V DRVDD = 3.3 V DRVDD = 1.8 V DRVDD = 2.5 V DRVDD = 3.3 V DRVDD = 1.8 V DRVDD = 2.5 V DRVDD = 3.3 V CLKP/CLKN inputs DLL delay line output ) ) Rev Page AD9961/AD9963 Min Typ Max Unit 1.2 V 1.7 V 2.0 V 0.5 V 0.7 V 0.8 V 1.35 V 2.05 V 2.4 V ...

  • Page 8

    ... AD9961/AD9963 ABSOLUTE MAXIMUM RATINGS Table 6. With Parameter Respect to RX33V, AUX33V RXGND TXVDD TXGND DRVDD DGND CLK33V EPAD RX18V, RX18VF RXGND DVDD18V EPAD CLK18V, DLL18V EPAD RXGND, TXGND, DGND, EPAD TXIP, TXIN, TXQP, TXQN TXGND RXIP, RXIN, RXQP, RXQN RXGND CS RESET , DGND ...

  • Page 9

    ... RXQP 3 RXQN RX18V 7 AD9961 RX33V 8 9 (TOP VIEW) RXCML 10 11 RXIN 12 RXIP 13 14 RESET 15 SCLK SDIO 18 Figure 2. AD9961 Pin Configuration Rev Page AD9961/AD9963 54 DLLFILT 53 DLL18V 52 DVDD18 51 DRVDD TXD0 47 TXD1 46 TXD2 45 TXD3 44 TXD4 43 TXD5 42 TXD6 41 TXD7 40 TXD8 ...

  • Page 10

    ... AD9961/AD9963 Pin No. Mnemonic Description 36 TRXCLK Qualifying Clock for the TRXD Bus. 37 TXCLK Qualifying Clock for the TXD Bus. It can be configured as either an input or output. 38 TXIQ/TXnRX Dual Function Pin. In half-duplex mode (TXnRX), this pin controls the direction of the TRX port. In full- duplex mode (TXIQ), this input signal indicates to which DAC the TxDAC input data is intended. ...

  • Page 11

    ... AUX33V AUXADCREF RXGND RXBIAS RX18VF RXGND LDO_EN NOTES 1. EXPOSED PAD MUST BE SOLDERED TO PCB. Table 9. AD9963 Pin Function Descriptions Pin No. Mnemonic Description 1 AUX33V Analog Supply for the Auxiliary ADC and Auxiliary DACs (3.3 V ± 10%, 1.8 V ± 10% If Auxiliary ADC Is Powered Down). 2 AUXADCREF Reference Output (or input) for Auxiliary ADC. ...

  • Page 12

    ... AD9961/AD9963 Pin No. Mnemonic Description 54 DLLFILT DLL Filter Output. 55 CLK18V Output of CLK18V Voltage Regulator. 56,57 CLKN, CLKP Differential Input Clock. 58 CLK33V Input to CLK18V and DLL18V Voltage Regulators (1 3.3 V). If LDOs are not being used, short Pin 58 to Pin 55. CLK33V must track TXVDD. 59, 60 TXQN, TXQP Complementary DAC Q Current Outputs ...

  • Page 13

    ... MHz, 1×, Digital Scale = 0 dBFS, TXVDD = 3.3 V DAC Over Full-Scale Current, Figure 7. Third Harmonic Distortion vs Over Full-Scale Current 2mA Over Full-Scale Current, Rev Page AD9961/AD9963 100 4mA 2mA I = 1mA ...

  • Page 14

    ... AD9961/AD9963 100 0dBFS 75 –3dBFS 70 65 –6dBFS (MHz) OUT Figure 10. Second Harmonic Distortion vs 125 MHz, 1×, Full-Scale Current = 2 mA, TXVDD = 3.3 V DAC 100 95 –6 dBFS dBFS 75 –3 dBFS (MHz) OUT Figure 11 ...

  • Page 15

    ... Figure 20. SNR/SFDR vs. Analog Input Level Figure 21. SNR/SFDR vs. Analog Input Level, f OUT Rev Page AD9961/AD9963 100 95 IDAC 3.3V CMOS SECOND HARMONIC (dBc IDAC 3.3V CMOS THIRD HARMONIC (dBc ...

  • Page 16

    ... AD9961/AD9963 1.2 1.0 0.8 INL 0.6 DNL 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 0 512 1024 1536 2048 2560 CODE Figure 22. Rx Path ADC, INL and DNL 155 IDAC, 125MHz, 4mA, 0dB 153 151 IDAC, 125MHz, 2mA, 0dB 149 147 145 QDAC, 125MHz, 1mA, 0dB 143 ...

  • Page 17

    ... Figure 32. AD9963 1.8 V CMOS IADC, 100 MSPS Single Tone AC –65 –70 –75 –80 –85 –90 100 120 140 Figure 33. AD9963 1.8 V CMOS IADC, 100 MSPS Single Tone AC Rev Page AD9961/AD9963 100 f (MHz ...

  • Page 18

    ... AD9961/AD9963 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code ...

  • Page 19

    ... ADC modes, and TxDAC power scaling. In full duplex mode, the AD9961/AD9963 use two 12-bit buses, along with qualifying clock signals, to transfer Rx path data and Tx path data. These two buses support either single data rate or double data rate data transfers ...

  • Page 20

    ... SCLK, determines the start of a communication cycle. There are two parts to a communication cycle with the AD9961/ AD9963. The first part writes a 16-bit instruction word into the AD9961/AD9963, coincident with the first 16 SCLK rising edges. The instruction word provides the AD9961/AD9963 serial control ports with information regarding the data transfer, which is the second part of the communication cycle ...

  • Page 21

    ... LSB First MSB First SUB SERIAL INTERFACE COMMUNICATIONS The AD9963/AD9961 have two registers that require a different communication sequence. These registers are 0x0F and 0x10. The write sequence for these two registers requires a write to Register 0x05, a write to the Register (0x0F or 0x10), and then a write to Register 0xFF ...

  • Page 22

    ... AD9961/AD9963 SCLK SDIO CS SCLK DON’T CARE SDIO DON’T CARE 16-BIT INSTRUCTION HEADER Figure 37. Serial Control Port Access—LSB First, 16-Bit Instruction, Two Bytes Data SCLK SDIO Table 13. Serial Control Port Timing Parameter Timing (Min, ns ...

  • Page 23

    ... TXQ_CHK[7:0] Chip ID[7:0] TXI_SLEEP TXQ_SLEEP CLK_PD DLLBIAS_PD CLK_LDO_PD RX_LDO_PD RX_LDO_ RXF_LDO_ DIG_LDO_ STAT STAT STAT TRXIQ_DRV Unused RXI_DCLK RXQ_DCLK Rev Page AD9961/AD9963 Bit 2 Bit 1 Reset LSB First ADDRQ RXCML ADC_OFFSET[5:0] SRRC_BP TXCLK_EN TXIQ_HILO TX_IFIRST RXIQ_HILO RX_IFIRST FIFO_OFFSET[2:0] SRRC_SCALE[4:0] INT0_SCALE[4:0] INT1_SCALE[4:0] DEC_SCALE[4:0] ...

  • Page 24

    ... AD9961/AD9963 Addr Default Bit 7 Bit 6 0x71 0x00 ADCCLKSEL DACCLKSEL 0x72 0x01 DLL_Locked 0x75 0x00 0x77 0x00 CONV_TIME[1:0] 0x78 Varies 0x79 Varies 0x7A 0x00 AUXADC_EN AUXADC_RESB 0x7B 0x00 TMPSNS_EN 0x7D 0x00 Unused 0x7E 0x00 Unused RXTrim_EN 0x7F 0x00 0x80 0x00 0x81 0x00 ...

  • Page 25

    ... DDR clocking mode. Rx data is driven out on both edges of the TRXCLK signal. 1: chooses bus rate clocking mode. Rx data is driven out on one edge of the TRXCLK signal. Unused RXCLK_MD[1:0] This sets the way the internal RXCLK signal in the chip is driven. 00: disabled. 01: disabled. 10: RXCLK is driven by internal Rx path clock. Rev Page AD9961/AD9963 ...

  • Page 26

    ... AD9961/AD9963 Register Register Name Address Bit( FIFO Alignment 0x33 2:0 FIFO Status 0x34 7:0 Tx Scale P 0x35 7:5 4:0 Tx Scale 0 0x36 7:5 4:0 Parameter Function 11: RXCLK is driven by the DLL output. Note that the RXCLK signal is present on the TRXCLK pin with one exception. In Half-Duplex 1-Clock mode, the RXCLK signal is present on the TRXCLK pin when Rx is active, but the TXCLK signal appears on the TRXCLK pin when TX is active ...

  • Page 27

    ... TX_INVQ 1: multiply Txdata for QDAC by −1. TX_INVI 1: multiply Txdata for IDAC by −1. Unused TX_DBLPW[2:0] Sets the pulse width of the Tx clock doubler. See Table 22 for details. RX_DBLPW[2:0] Sets the pulse width of the Rx clock doubler. See Table 22 for details. Rev Page AD9961/AD9963 ...

  • Page 28

    ... AD9961/AD9963 Register Register Name Address Bit(s) Rx Data Interface 0x3F DAC12 Config 0x40 3 DAC12A MSBs 0x41 7:0 DAC12A LSBs 0x42 7:4 3:0 DAC12B MSBs 0x43 7:0 DAC12B LSBs 0x44 7:4 3:0 DAC10B Config 0x45 7 6:5 4:2 Parameter Function Unused RX_CLK 0: when SINGLERX is active, use Q side clock. ...

  • Page 29

    ... PRN output. RX_INSEL 0: selects pattern input from internal pattern generator. 1: selects pattern from the external pins of the Rx path. RX_CONT 0: runs the BIST for 512 cycles. 1: runs the BIST continuously. Rev Page AD9961/AD9963 ...

  • Page 30

    ... AD9961/AD9963 Register Register Name Address Bit( TXI Check MSB 0x52 7:0 TXI Check LSB 0x53 7:0 TXQ Check MSB 0x54 7:0 TXQ Check LSB 0x55 7:0 Version 0x5C 7:0 Power Down 0 0x60 Power Down 1 0x61 LDO Status ...

  • Page 31

    ... Adjusts the on-chip reference voltage and output at REFIO. The transmit DAC full-scale currents and the auxiliary DAC full-scale voltages are proportional to the REFIO voltage. The approximate REFIO output voltage by code is: 000000 1.0 V. REF 000001 1.00625 V. REF … 011111 1.19375 V. REF Rev Page AD9961/AD9963 ...

  • Page 32

    ... AD9961/AD9963 Register Register Name Address Bit(s) DLL Control 0 0x71 3:0 DLL Control 1 0x72 7 6:5 4:0 DLL Control 2 0x75 7:4 3 2:0 Aux ADC Config 0x77 7:6 and Conversion Start 5:3 2:0 Parameter Function 100000 0.8 V. REF 100001 0.80625 V. REF … 111111 : V = 0.99375 V. REF ADCCLKSEL 1: selects DLL output as the ADC sampling clock. ...

  • Page 33

    ... Unused Unused RX_FSADJ[4:0] This parameter adjusts the full-scale input voltage range of the Rx path ADCs. The peak-to-peak input voltage range can be set as follows: 10000: 1.25 V. 10001:1.27 V. 10010: 1.29 V. 10011: 1.31 V. … 11111: 1.54 V. 00000: 1.56 V. 00001: 1.58 V. … 01110: 1.873 V. 01111: 1.875 V. Rev Page AD9961/AD9963 ...

  • Page 34

    ... AD9961/AD9963 Register Register Name Address Bit(s) Rx ADC Trim Ctrl 0x7E 3:1 0 IGAIN CAL MSBs 0x7F 7:0 IGAIN CAL LSBS 0x80 7:3 2:1 0 IGAIN CAL MSBs 0x81 7:0 IGAIN CAL LSBs 0x82 7:3 2:1 0 IGAIN CAL LSBS 0xFF 7:1 0 Parameter Function Unused RXTrim_EN 1: enables ADC gain calibration. RXTrim_Fine 1: decreases the step size (increases resolution) of the gain calibration adjustment ...

  • Page 35

    ... SNR. Decreasing the input voltage range leads to better linearity. RXBIAS The AD9961/AD9963 provide the user with the option to place a 10 kΩ resistor between the RXBIAS pin and ground. This resistor is used to set the master current reference of the ADC core ...

  • Page 36

    ... AD9961/ AD9963 In this application, the ADF4602 is setting the common-mode input voltage of the AD9963 ADCs. The input common-mode buffer of the AD9963 should be disabled (set Register 0x7E, Bit avoid contention with the ADF4602 output driver. DECIMATION FILTER AND DIGITAL OFFSET Decimation Filter The I and Q receive paths each have a bypassable 2× ...

  • Page 37

    ... Write 0x01 into Register 0xFF. This updates the data path Value registers and applies the offset to the data Write 0x00 into Register 0x05. This returns the SPI to the −32 normal addressing mode. 72 −140 252 −422 682 −1086 1778 −3284 10364 16384 Rev Page AD9961/AD9963 ...

  • Page 38

    ... AD9961/AD9963 TRANSMIT PATH Tx Path General Description The transmit section consists of two complete paths of interpolation filters stages, each followed by a high speed current output DAC. A data assembler receives interleaved data from one of two digital interface ports, and de-interleaves and buffers the data before supplying the data samples into the two datapaths. The interpolation filter bank consists of three stages that can be completely bypassed or cascaded to provide 2× ...

  • Page 39

    ... FIFO by the WRCLK signal at the quadrature data input rate DATA and Q samples are interleaved. Figure 52 shows the block diagram of the transmit path data flow in full-duplex mode. Also shown in the diagram are the input data clocking options and the clock doubler selections. Rev Page AD9961/AD9963 Upper Coefficient H(53) H(52) H(51) H(50) H(49) H(48) H(47) ...

  • Page 40

    ... The DACs are powered through the TXVDD pin and can operate over a 1 3.3 V supply range. To facilitate interfacing the output of the AD9961/AD9963 directly to a range of common- mode levels, an internal bias voltage is made available through the TXCML pin. ...

  • Page 41

    ... The adjustment range of the fine scale adjust (GAIN2) is about ±2.5%. Figure 56 and Figure 57 show the resulting gain scaling vs. the GAIN1 and GAIN2 parameters. Rev Page AD9961/AD9963 REFIO Pin Register Setting Connect 0.1 μF capacitor Register 0x60, Bit (default) ...

  • Page 42

    ... Figure 57. Typical DAC Full-Scale Current vs. GAIN2 Code TRANSMIT DAC OUTPUTS The optimum noise and distortion performances of the AD9961/ AD9963 are realized when they are configured for differential operation. The common-mode error sources of the DAC outputs are significantly reduced by the common-mode rejection of a transformer or differential amplifier ...

  • Page 43

    ... C Figure 60. Circuit for Setting TXCML Level Using R Transmit DAC Output Circuit Configurations The following section illustrates some typical output configu- rations for the AD9961/AD9963 transmit DACs. Unless otherwise noted assumed that I OUTFS 2.0 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. ...

  • Page 44

    ... ADF4602 R FB other wireless communications applications. The ADF4602 Tx baseband inputs have a nominal input common-mode voltage – requirement of 1.2 V. The AD9963 can be dc coupled to the ADA4841-2 ADF4602 as shown in Figure 64. When configured for full-scale current, the output swing of the circuit ppd V OUT centered at 1 ...

  • Page 45

    ... AUXDIV ADCCLKSEL DCS_BP ÷ADCDIV 0 1 DCS DLL ÷DLLDIV M N DLLCLK 1 0 DACCLKSEL ÷AUXDIV Figure 65. Clock Distribution Diagram Rev Page AD9961/AD9963 Address Values Register 0 or1 0x66 0x66 0x71 0x71 0x71 1, 2, 3,…, 32 0x72 0x72 2J ...

  • Page 46

    ... Below 75 MHz, the DCS should be bypassed. The DCS is bypassed by setting Register 0x66, Bit 2 high. CLOCK MULTIPLICATION USING THE DLL The AD9961/AD9963 contain a recirculating DLL, as shown in Figure 70. This circuit allows the incoming CLK signal (REFCLK multiplied by a programmable M/N factor. ...

  • Page 47

    ... Table 22. Z 68nF RXDBLSEL TX_DBLPW[2:0] Register 0x3E, Register 0x39, Bits[5:3] Bit 1 111 Rev Page AD9961/AD9963 1 RX_DBLPW[2:0] DCS_BP Register 0x3E, Register 0x66, Bits[2:0] Bit 2 111 1 111 1 110 1 101 1 100 1 011 ...

  • Page 48

    ... I data aligned with TRXIQ being low. The IQ pairing and data to TRXIQ alignment relationships create four possible timing modes. The AD9961/AD9963 enable any of these four modes to be sourced from the device. The data pairing order is controlled by the RX_IFIRST bit. The phase relationship between the Rx data and the RXIQ signal is controlled by the RXIQ_HILO bit ...

  • Page 49

    ... TXIQ signal phase relationships. This creates four possible timing modes. The AD9961/AD9963 can be configured to accept data in any of these four modes. The data pairing order is controlled by the TX_IFIRST bit. The data to TXIQ phase relationship is controlled by the TXIQ_HILO bit ...

  • Page 50

    ... TXD[11 :0] TXD[11 :0] TXD[11 :0] HALF-DUPLEX MODE t The AD9961/AD9963 offer a half-duplex mode enabling a HD reduced width digital interface. In half-duplex mode, the transmit and receive ports are multiplexed onto the TRXD, TRXIQ, and TRXCLK lines. The direction of the bus can be controlled by either the TXIQ/TXnRX pin (for the rest of this section referred to as simply the TXnRX pin) or the serial port configuration registers ...

  • Page 51

    ... The timing of the bus turnaround is shown in the Figure 83 and Figure 84. TXnRX TRXIQ TRXD[11:0] Figure 83. Half-Duplex Bus Turnaround TXnRX Tx Bus Function High-Z TRXIQ High-Z High-Z High-Z TRXD[11:0] Tx Bus Function High-Z High-Z t TXRDY HIGH-Z HIGH-Z Rev Page AD9961/AD9963 t TXRDY HIGH-Z HIGH-Z Figure 84. Half-Duplex Bus Turnaround ...

  • Page 52

    ... AD9961/AD9963 AUXILIARY CONVERTERS The AD9961/AD9963 have two fast settling servo DACs, along with an analog input and two analog I/O pins. All of the auxiliary converters run off a dedicated supply pin. The input and output compliance ranges depend on the voltage supplied. AUXILIARY ADC The auxiliary ADC is a 12-bit SAR converter that is accessed and controlled through the serial port registers (Register 0x77 through Register 0x7B) ...

  • Page 53

    ... ADC to reach an optimum operating condition. AUXILIARY DACs The AD9963 has two 10-bit auxiliary DACs and two 12-bit auxiliary DACs suitable for calibration and control functions. The DACs have voltage outputs with selectable full-scale voltages and output ranges. The auxiliary DACs are configured and updated through the serial port interface ...

  • Page 54

    ... AD9961/AD9963 The curves in Figure 89 represent four of the possible DAC transfer functions with the full-scale voltage of 3.0 V and spans of 0.5 V, 1.0 V, 1.5 V, and 2.0 V. The curves in Figure 90 represent four of the possible DAC transfer functions with the full-scale voltage of 1.5 V and spans of 0.5 V, 1.0 V, 1.5 V, and 2 ...

  • Page 55

    ... POWER SUPPLIES The AD9961/AD9963 power distributions are shown in Figure 93. The functional blocks labeled Rx ANLG, Rx ADCs, SPI and digital core, clocking, and DLL operate from 1.8 V supplies. The functional blocks labeled Tx DACs, AUX DACs and digital I/O operate over a supply voltage range from 1 3.3 V. The auxiliary ADC operates from a 3 ...

  • Page 56

    ... AD9961/AD9963 80 RX18V RX18VF (MHz) ADC Figure 96. I and I vs Both ADCs Enabled RX18V RX18VF ADC 4mA 2mA 1mA 100 f (MHz) DAC Figure 97 FSC = 1 mA, 2 mA, 4 mA, TXVDD = 3.3 V TXVDD ...

  • Page 57

    ... Auxiliary ADC enabled All other supplies powered from external 1.8 V supplies. Table 30. Example Power Supply Currents Supply RX18V RX18VF TXVDD CLKVDD18V DLL18V DVDD18V (Rx) DVDD18V (Tx) DRVDD AUX33V 80 90 100 Total (1.8 V) Total (3.3 V) Rev Page AD9961/AD9963 Typical Current (mA) Typical Power (mW) 74 133 5.2 9.5 7.5 13 ...

  • Page 58

    ... Temperature Range AD9961BCPZ −40°C to +85°C AD9961BCPZRL −40°C to +85°C AD9963BCPZ −40°C to +85°C AD9963BCPZRL −40°C to +85°C AD9961-EBZ −40°C to +85°C AD9963-EBZ −40°C to +85°C HSC-DAC-EVALCZ −40°C to +85° RoHS Compliant Part. 0.60 0.42 0.24 54 0.50 9 ...

  • Page 59

    ... NOTES Rev Page AD9961/AD9963 ...

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