AD6642 Analog Devices, AD6642 Datasheet - Page 19

• Manufacturer Part Number: AD6642
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins, as shown in Figure 39. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516
jitter performance.
CLOCK
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 40. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516 clock
drivers offer excellent jitter performance.
CLOCK
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applica-
tions, the CLK+ pin should be driven directly from a CMOS
gate, and the CLK− pin should be bypassed to ground with a
0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 41).
CLOCK
CLK+ can be driven directly from a CMOS gate. Although
the CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages of up to 3.6 V, making the
selection of the drive logic voltage very flexible (see Figure 42).
CLOCK
CLOCK
INPUT
INPUT
INPUT
INPUT
INPUT
Figure 41. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
50kΩ
50kΩ
Figure 39. Differential PECL Sample Clock (Up to 625 MHz)
Figure 40. Differential LVDS Sample Clock (Up to 625 MHz)
50Ω
1
50Ω RESISTOR IS OPTIONAL.
0.1µF
1
0.1µF
0.1µF
50kΩ
0.1µF
0.1µF
50kΩ
V
CC
1kΩ
1kΩ
AD951x
PECL DRIVER
AD951x
LVDS DRIVER
AD951x
CMOS DRIVER
240Ω
0.1µF
clock drivers offer excellent
OPTIONAL
240Ω
100Ω
39kΩ
100Ω
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
CLK+
CLK–
CLK+
CLK–
CLK+
CLK–
ADC
ADC
ADC
Rev. A | Page 19 of 32
Input Clock Divider
The AD6642 contains an input clock divider with the ability to
divide the input clock by integer values from 1 to 8.
The AD6642 clock divider can be synchronized using the
external SYNC input. Bit 1 of Register 0x3A enables the clock
divider to be resynchronized on every SYNC signal. A valid
SYNC causes the clock divider to reset to its initial state. This
synchronization feature allows multiple parts to have their clock
dividers aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD6642 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock signal
with a nominal 50% duty cycle. This allows the user to provide a
wide range of clock input duty cycles without affecting the per-
formance of the AD6642. Noise and distortion performance are
nearly flat for a wide range of duty cycles with the DCS enabled.
Jitter in the rising edge of the input is still of paramount concern
and is not easily reduced by the internal stabilization circuit. The
duty cycle control loop does not function for clock rates less
than 40 MHz nominally. The loop has a time constant asso-
ciated with it that must be considered in applications in which
the clock rate can change dynamically. A wait time of 1.5 μs to
5 μs is required after a dynamic clock frequency increase or
decrease before the DCS loop is relocked to the input signal.
During the time period that the loop is not locked, the DCS
loop is bypassed, and internal device timing is dependent on the
duty cycle of the input clock signal.
CLOCK
INPUT
Figure 42. Single-Ended 3.3 V CMOS Input Clock (Up to 200 MHz)
1
50Ω RESISTOR IS OPTIONAL.
50Ω
0.1µF
1
V
CC
1kΩ
1kΩ
AD951x
CMOS DRIVER
OPTIONAL
100Ω
0.1µF
0.1µF
CLK+
CLK–
AD6642
ADC