AD6642 Analog Devices, AD6642 Datasheet - Page 25

• Manufacturer Part Number: AD6642
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

SERIAL PORT INTERFACE (SPI)
The AD6642 serial port interface (SPI) allows the user to con-
figure the receiver for specific functions or operations through a
structured internal register space. The SPI provides added flexibility
and customization, depending on the application. Addresses are
accessed via the serial port and can be written to or read from
via the port. Memory is organized into bytes that can be further
divided into fields, which are documented in the Memory Map
section. For detailed operational information, see Application
Note AN-877, Interfacing to High Speed ADCs via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of the AD6642: SCLK, SDIO, and CSB
(see Table 12). SCLK (a serial clock) is used to synchronize the
read and write data presented from and to the AD6642. SDIO
(serial data input/output) is a bidirectional pin that allows data
to be sent to and read from the internal memory map registers.
CSB (chip select bar) is an active low control that enables or
disables the read and write cycles.
Table 12. Serial Port Interface Pins
Pin
SCLK
SDIO
CSB
The falling edge of the CSB pin, in conjunction with the rising
edge of the SCLK pin, determines the start of the framing. An
example of the serial timing can be found in Figure 51 (for
symbol definitions, see Table 5).
CSB can be held low indefinitely, which permanently enables
the device; this is called streaming. CSB can stall high between
bytes to allow for additional external timing. When CSB is tied
high, SPI functions are placed in high impedance mode.
SCLK
SDIO
CSB
DON’T
CARE
Function
Serial clock. Serial shift clock input. SCLK is used to
synchronize serial interface reads and writes.
Serial data input/output. Bidirectional pin that serves
as an input or an output, depending on the instruction
being sent and the relative position in the timing frame.
Chip select bar (active low). This control gates the read
and write cycles.
DON’T
CARE
t
S
R/W
t
DS
W1
W0
t
DH
A12
t
HIGH
A11
Figure 51. Serial Port Interface Timing Diagram
t
LOW
A10
A9
t
CLK
Rev. A | Page 25 of 32
A8
A7
During an instruction phase, a 16-bit instruction is transmitted.
The first bit of the first byte in a serial data transfer frame indicates
whether a read command or a write command is issued. Data
follows the instruction phase, and its length is determined by
the W0 and W1 bits. All data is composed of 8-bit words.
The instruction phase determines whether the serial frame is a
read or write operation, allowing the serial port to be used both
to program the chip and to read the contents of the on-chip
memory. If the instruction is a read operation, the serial data
input/output (SDIO) pin changes direction from an input to an
output at the appropriate point in the serial frame.
Data can be sent in MSB first mode or in LSB first mode.
MSB first is the default mode on power-up and can be changed
via the SPI port configuration register. For more information
about this and other features, see Application Note AN-877,
Interfacing to High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 12 constitute the physical interface
between the user programming device and the serial port of the
AD6642. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during the write phase and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in Application Note AN-812, Micro-
controller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the AD6642 is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade AD6642 performance. If the on-board SPI bus is used
for other devices, it may be necessary to provide buffers between
this bus and the AD6642 to prevent these signals from transi-
tioning at the receiver inputs during critical sampling periods.
D5
D4
D3
D2
D1
D0
t
H
DON’T CARE
DON’T CARE
AD6642