AD9609 Analog Devices, AD9609 Datasheet - Page 19

• Manufacturer Part Number: AD9609
• Description: 10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9609

• Resolution (bits): 10bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

VOLTAGE REFERENCE
A stable and accurate 1.0 V voltage reference is built into the
AD9609. The VREF can be configured using either the internal
1.0 V reference or an externally applied 1.0 V reference voltage.
The various reference modes are summarized in the sections that
follow. The Reference Decoupling section describes the best
practices for PCB layout of VREF.
Internal Reference Connection
A comparator within the AD9609 detects the potential at the
SENSE pin and configures the reference into two possible
modes, which are summarized in Table 10. If SENSE is grounded,
the reference amplifier switch is connected to the internal resistor
divider (see Figure 42), setting VREF to 1.0 V.
In either internal or external reference mode, the maximum
input range of the ADC can be varied by configuring SPI
Address 0x18 as shown in Table 11, resulting in a selectable
differential span from 1 V p-p to 2 V p-p.
If the internal reference of the AD9609 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 43 shows
how the internal reference voltage is affected by loading.
Table 10. Reference Configuration Summary
Selected Mode
Fixed Internal Reference
Fixed External Reference
Table 11. Scaled Differential Span Summary
Selected Mode
Fixed Internal or External Reference
Fixed Internal or External Reference
Fixed Internal or External Reference
Fixed Internal or External Reference
Fixed Internal or External Reference
1.0µF
Figure 42. Internal Reference Configuration
0.1µF
SENSE
VREF
VIN+
VIN–
SELECT
LOGIC
SENSE Voltage (V)
AGND to 0.2
AVDD
ADC
Resulting VREF (V)
1.0 (internal or external)
1.0 (internal or external)
1.0 (internal or external)
1.0 (internal or external)
1.0 (internal or external)
0.5V
CORE
ADC
Resulting VREF (V)
1.0 internal
1.0 applied to external VREF pin
Rev. 0 | Page 19 of 32
SPI Register 0x18 (Hex)
0xC0
0xC8
0xD0
0xD8
0xE0
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 44 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 27). The internal buffer generates the posi-
tive and negative full-scale references for the ADC core. Therefore,
the external reference must be limited to a maximum of 1.0 V.
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–1
–2
–3
–4
–5
–6
0
4
3
2
1
0
–40
0
0.2
Figure 43. VREF Accuracy vs. Load Current
–20
0.4
Figure 44. Typical VREF Drift
Resulting Differential Span (V p-p)
2.0
2.0
0.6
VREF ERROR (mV)
0
LOAD CURRENT (mA)
Resulting Differential Span (V p-p)
1.0
1.14
1.33
1.6
2.0
TEMPERATURE (°C)
INTERNAL VREF = 0.996V
0.8
20
1.0
1.2
40
1.4
1.6
60
1.8
AD9609
80
2
.0