AD9609 Analog Devices, AD9609 Datasheet - Page 22

• Manufacturer Part Number: AD9609
• Description: 10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9609

• Resolution (bits): 10bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9609
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 53, the analog core power dissipated by the
AD9609 is proportional to its sample rate. The digital power
dissipation of the CMOS outputs are determined primarily by
the strength of the digital drivers and the load on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
where N is the number of output bits (22, in the case of the
AD9609).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of f
lished by the average number of output bits switching, which
is determined by the sample rate and the characteristics of the
analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 53 was
taken using the same operating conditions as those used for the
Typical Performance Characteristics, with a 5 pF load on each
output driver.
In SPI mode, the AD9609 can be placed in power-down mode
directly via the SPI port, or by using the programmable external
MODE pin. In non-SPI mode, power-down is achieved by assert-
ing the PDWN pin high. In this state, the ADC typically dissipates
500 μW. During power-down, the output drivers are placed in a
high impedance state. Asserting PDWN low (or the MODE pin
in SPI mode) returns the AD9609 to its normal operating mode.
Note that PDWN is referenced to the digital output driver
supply (DRVDD) and should not exceed that supply voltage.
IDRVDD = V
85
80
75
70
65
60
55
50
45
40
35
10
Figure 53. AD9609 Analog Core Power vs. Clock Rate
CLK
20
/2. In practice, the DRVDD current is estab-
AD9609-20
DRVDD
30
× C
CLOCK RATE (MSPS)
AD9609-40
LOAD
40
× f
CLK
AD9609-65
50
× N
60
AD9609-80
70
80
Rev. 0 | Page 22 of 32
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map section
for more details.
DIGITAL OUTPUTS
The AD9609 output drivers can be configured to interface with
1.8 V to 3.3 V CMOS logic families. Output data can also be
multiplexed onto a single output bus to reduce the total number
of traces required.
The CMOS output drivers are sized to provide sufficient output
current to drive a wide variety of logic families. However, large
drive currents tend to cause current glitches on the supplies and
may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
The output data format can be selected to be either offset binary
or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Table 12).
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI control.
Table 12. SCLK/DFS and SDIO/PDWN Mode Selection
(External Pin Mode)
Voltage at Pin
AGND
DRVDD
Digital Output Enable Function (OEB)
When using the SPI interface, the data outputs and DCO can be
independently three-stated by using the programmable external
MODE pin. The MODE pin (OEB) function is enabled via
Bits[6:5] of Register 0x08.
If the MODE pin is configured to operate in traditional OEB
mode, and the MODE pin is low, the output data drivers and
DCOs are enabled. If the MODE pin is high, the output data
drivers and DCOs are placed in a high impedance state. This
OEB function is not intended for rapid access to the data bus.
Note the MODE pin is referenced to the digital output driver
supply (DRVDD) and should not exceed that supply voltage.
SCLK/DFS
Offset binary (default)
Twos complement
SDIO/PDWN
Normal operation
(default)
Outputs disabled