AD9609 Analog Devices, AD9609 Datasheet - Page 20

• Manufacturer Part Number: AD9609
• Description: 10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9609

• Resolution (bits): 10bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9609
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9609 sample clock
inputs, CLK+ and CLK−, with a differential signal. The signal
is typically ac-coupled into the CLK+ and CLK− pins via a
transformer or capacitors. These pins are biased internally
(see Figure 45) and require no external bias.
Clock Input Options
The AD9609 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of great concern, as described in the Jitter Considerations section.
Figure 46 and Figure 47 show two preferred methods for clock-
ing the AD9609 (at clock rates up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF transformer or an RF balun.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is
recommended for clock frequencies from 10 MHz to 200 MHz.
The back-to-back Schottky diodes across the transformer/
balun secondary limit clock excursions into the AD9609 to
approximately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9609 while
preserving the fast rise and fall times of the signal that are
critical to a low jitter performance.
CLOCK
INPUT
CLOCK
INPUT
Figure 46. Transformer-Coupled Differential Clock (Up to 200 MHz)
Figure 47. Balun-Coupled Differential Clock (Up to 625 MHz)
CLK+
50Ω
0.1µF
50Ω
1nF
Figure 45. Equivalent Clock Input Circuit
1nF
2pF
100Ω
ADT1-1WT, 1:1 Z
Mini-Circuits
XFMR
0.1µF
AVDD
0.9V
®
0.1µF
0.1µF
0.1µF
0.1µF
SCHOTTKY
SCHOTTKY
HSMS2822
HSMS2822
DIODES:
DIODES:
2pF
CLK+
CLK–
CLK–
CLK+
CLK–
ADC
ADC
Rev. 0 | Page 20 of 32
CLOCK
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 48. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516/AD9517
excellent jitter performance.
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 49. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517
clock drivers offer excellent jitter performance.
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK− pin to ground with a 0.1 μF capacitor (see
Figure 50).
Input Clock Divider
The AD9609 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8.
Optimum performance can be obtained by enabling the inter-
nal duty cycle stabilizer (DCS) when using divide ratios other
than 1, 2, or 4.
CLOCK
CLOCK
CLOCK
CLOCK
INPUT
INPUT
INPUT
INPUT
INPUT
Figure 50. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
50kΩ
50kΩ
Figure 49. Differential LVDS Sample Clock (Up to 625 MHz)
Figure 48. Differential PECL Sample Clock (Up to 625 MHz)
50Ω
1
50Ω RESISTOR IS OPTIONAL.
0.1µF
1
0.1µF
0.1µF
50kΩ
0.1µF
0.1µF
50kΩ
V
CC
1kΩ
1kΩ
LVDS DRIVER
PECL DRIVER
CMOS DRIVER
AD951x
AD951x
AD951x
240Ω
OPTIONAL
240Ω
100Ω
0.1µF
100Ω
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
clock drivers offer
0.1µF
CLK+
CLK–
CLK+
CLK–
CLK+
CLK–
ADC
ADC
ADC