AD9609 Analog Devices, AD9609 Datasheet - Page 29

• Manufacturer Part Number: AD9609
• Description: 10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9609

• Resolution (bits): 10bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Addr
(Hex)
0x0E
0x10
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x24
0x2A
1.1. AD9609-Specific Customer SPI Control
0x101
Register Name
BIST enable
Offset adjust
Output mode
Output adjust
Output phase
Output delay
VREF
USER_PATT1_LSB
USER_PATT1_MSB
USER_PATT2_LSB
USER_PATT2_MSB
BIST signature LSB
OR/MODE select
USR2
Bit 7
(MSB)
8-bit device offset adjustment, Bits[7:0] (local)
Offset adjust in LSBs from +127 to −128 (twos complement format)
00 = 3.3 V CMOS
10 = 1.8 V CMOS
3.3 V DCO
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
DCO
Output
polarity
0 =
normal
1 =
inverted
Enable
DCO
delay
Reserved =11
B7
B15
B7
B15
Open
Open
1
Bit 6
Open
Open
Open
B6
B14
B6
B14
Open
Bit 5
Open
Open
1.8 V DCO
drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes
(default)
11 = 4 stripes
Open
Enable
data
delay
Internal VREF adjustment,
Bits[2:0]
000 = 1.0 V p-p
001 = 1.14 V p-p
010 = 1.33 V p-p
011 = 1.60 V p-p
100 = 2.0 V p-p
B5
B13
B5
B13
Open
Open
Bit 4
Open
Output
disable
Open
B4
B12
B4
B12
BIST signature, Bits[7:0]
Open
Rev. 0 | Page 29 of 32
Open
Bit 3
Open
Open
3.3 V data
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
Open
B3
B11
B3
B11
Open
Enable
GCLK
detect
BIST
Output
Bit 2
INIT
invert
Input clock phase adjust, Bits[2:0]
(Value is number of input clock
cycles of phase delay)
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
DCO/data delay[2:0]
000 = 0.56 ns
001 = 1.12 ns
010 = 1.68 ns
011 = 2.24 ns
100 = 2.80 ns
101 = 3.36 ns
110 = 3.92 ns
111 = 4.48 ns
B2
B10
B2
B10
Open
Run
GCLK
Bit 1
Open
00 = offset binary
01 = twos complement
10 = gray code
11 = offset binary
1.8 V data
drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes (default)
11 = 4 stripes
B1
B9
B1
B9
Open
Open
Open
BIST enable
0 = MODE
Bit 0
(LSB)
B0
B8
B0
B8
1 = OR
(default)
Disable SDIO
pull-down
Default
Value
(Hex)
0x00
0x00
0x00
0x22
0x00
0x00
0xE0
0x00
0x00
0x00
0x00
0x00
0x01
0x88
Comments
When Bit 0 is set,
the built in self-test
function is initiated.
Device offset trim
Configures the
outputs and the
format of the data
Determines CMOS
output drive
strength properties
On devices that
utilize global clock
divide, determines
which phase of the
divider output is
used to supply the
output clock;
internal latching is
unaffected
Sets the fine output
delay of the output
clock but does not
change internal
timing
Selects and/or
adjusts the VREF
full-scale span
User-defined
pattern, 1 LSB
User-defined
pattern, 1 MSB
User-defined
pattern, 2 LSB
User-defined
pattern, 2 MSB
Least significant
byte of BIST
signature, read only
Selects I/O
functionality in
conjunction with
Address 0x08 for
MODE (input) or OR
(output) on external
Pin 23
Enables internal
oscillator for clock
rates <5 MHz
AD9609