AD7147A Analog Devices, AD7147A Datasheet

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... GPIO. There set the voltage level for the serial interface independent of V The AD7147A is available in a 25-ball, 2.3 mm × 2.1 mm WLCSP and operates from a 2 3.6 V supply. The operating current consumption in low power mode is typically 28.96 μA for 13 sensors ...

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... General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Average Current Specifications .................................................. 4 SPI Timing Specifications (AD7147A) ...................................... Timing Specifications (AD7147A-1) .................................. 6 Absolute Maximum Ratings ............................................................ 7 ESD Caution .................................................................................. 7 Pin Configurations and Function Descriptions ........................... 8 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 11 Capacitance Sensing Theory ..................................................... 11 BIAS Pin ....................................................................................... 12 Operating Modes ........................................................................ 12 Capacitance-to-Digital Converter ...

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... V OUT DRIVE = 3.6 V DRIVE = 3.6 V DRIVE + V , Register 0x00, Bits[15:14 DRIVE + V , Register 0x00, Bits[15:14 DRIVE + V , Register 0x00, Bits[15:14 DRIVE + V , Register 0x00, Bits[15:14 DRIVE + V , decimation = 256; CC DRIVE + V , Register 0x00, Bits[15:14 DRIVE AD7147A CC ...

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... AD7147A AVERAGE CURRENT SPECIFICATIONS Table 2. Typical Average Current in Low Power Mode Low Power Decimation Mode Delay Rate 1 200 ms 64 22.27 128 27.95 256 39.15 400 ms 64 18.89 128 21.76 256 27.45 600 ms 64 17.76 128 19.68 256 23.49 800 ms 64 17.20 128 18.63 256 21. 3 25°C, load = 50 pF Table 3. Maximum Average Current in Low Power Mode ...

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... SPI TIMING SPECIFICATIONS (AD7147A −40°C to +85°C, sample tested at 25°C to ensure compliance noted. All input signals are specified with t Table 4. SPI Timing Specifications Parameter Limit f 5 SCLK ...

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... AD7147A TIMING SPECIFICATIONS (AD7147A- −40°C to +85°C, sample tested at 25°C to ensure compliance noted. All input signals timed from a voltage level of 1 Table Timing Specifications Parameter Limit f 400 SCLK 100 4 t 300 ...

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... 0.3 V DRIVE maximum rating conditions for extended periods may affect 10 mA device reliability. ESD CAUTION −40°C to +105°C −65°C to +150°C 150° 65°C/W 260°C (± 0.5°C) 300°C Rev Page AD7147A ...

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... INT GPIO CIN1 CIN3 CIN5 A ADD1 TP CIN2 CIN6 CIN7 B SCLK V CIN4 CIN8 CIN9 DRIVE C ADD0 V CIN0 CIN10 CIN11 CC D SDA GND BIAS AC CIN12 SHIELD E TOP VIEW (BALL SIDE DOWN) Not to Scale NOTES 1. TP DENOTES FACTORY TEST POINT. Figure 6. AD7147A-1 Pin Configuration ...

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... CC Figure 10. Low Power Supply Current vs. Supply Voltage, Decimation Rate = 64 2.5 2.0 1.5 1.0 0.5 0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 V (V) CC Figure 11. Shutdown Supply Current vs. Supply Voltage 1150 1100 1050 1000 950 900 0 100 200 300 400 AC CAPACITIVE LOAD (pF) SHIELD Figure 12. Supply Current vs. Capacitive Load on AC AD7147A 600ms 3.5 3.7 3.5 3.6 500 SHIELD ...

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... AD7147A 58,000 56,000 54,000 52,000 50,000 48,000 46,000 44,000 42,000 40,000 0 100 200 300 AC CAPACITIVE LOAD (pF) SHIELD Figure 13. CDC Code vs. Capacitive Load on AC 960 940 3.6V 920 900 3.3V 880 860 840 820 2.6V 800 780 –60 –40 – TEMPERATURE (°C) Figure 14. Supply Current vs. Temperature ...

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... The external sensors consist of an electrode on a single- or multiple-layer PCB that interfaces directly to the AD7147A. The AD7147A can be set up to implement any set of input sensors by programming the on-chip registers. The registers can also be programmed to control features such as averaging, offsets, and gains for each of the external sensors ...

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... STAGEx_LOW_THRESHOLD an open-source basis. BIAS PIN This pin is connected internally to a bias node of the AD7147A. To ensure correct operation of the AD7147A, connect a 100 nF capacitor between the BIAS pin and ground. The voltage seen at the BIAS pin is V OPERATING MODES The AD7147A has three operating modes ...

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... See the CDC Conversion Sequence Time section for more information.) The time for the AD7147A to transition from a full power state to a reduced power state after the user stops touching the external sensors is configurable. The PWR_DOWN_TIMEOUT bits in ...

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... CAPACITANCE SENSOR OFFSET CONTROL There are two programmable DACs on board the AD7147A to null the effect of any stray capacitances on the CDC measurement. These offsets are due to stray capacitance to ground. A simplified block diagram in Figure 23 shows how to apply the STAGEx_AFE_OFFSET registers to null the offsets ...

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... STAGE3 + CDC – STAGE4 + CDC – STAGE5 + CDC – SLIDER STAGE6 + CDC – STAGE7 + – CDC Figure 25. Sequencer Setup for Sensors Rev Page AD7147A SEQUENCER STAGE8 B1 + CDC – STAGE9 B2 + CDC – B3 AD7147A SEQUENCER STAGE10 + CDC – STAGE11 + CDC – AD7147A ...

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... Bank 3. The host processes the data read back from these registers using a software algorithm to determine position information. In addition to the results registers in Bank 3, the AD7147A provides the 16-bit CDC output data directly, starting at Address 0x00B of Bank 1. Reading back the CDC 16-bit conversion data register allows for customer-specific application data processing ...

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... Connecting a CINx input pin to the negative CDC input results in a decrease in CDC output code when the corresponding sensor is activated. The AD7147A performs a sequence of 12 conversions. The multi- plexer can have different settings for each of the 12 conversions. For example, CIN0 is connected to the negative CDC input for conversion STAGE1, left floating for conversion STAGE1, and so on, for all 12 conversion stages ...

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... This means that the ambient value stored on the AD7147A no longer represents the actual ambient value. In this case, even when the user is not in close proximity to the sensor, the prox- imity flag may still be set ...

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... Comparator 1 (see Figure 33). USER LEAVES SENSOR AREA CALDIS CALIBRATION DISABLED USER LEAVES SENSOR AREA CALDIS CALIBRATION DISABLED LP_CONV_DELAY. CONV_LP CONV_FP × LP_PROXIMITY_CNT × 4). Rev Page AD7147A t CONV_FP CALIBRATION ENABLED t CONV_LP CALIBRATION ENABLED ...

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... AD7147A USER APPROACHES SENSOR USER LEAVES SENSOR AREA CDC CONVERSION SEQUENCE (INTERNAL) PROXIMITY DETECTION (INTERNAL) CALIBRATION CALIBRATION DISABLED (INTERNAL) RECALIBRATION COUNTER (INTERNAL) NOTES 1. SEQUENCE CONVERSION TIME × FP_PROXIMITY_CNT × 16. CALDIS CONV_FP RECAL_TIMEOUT CONV_FP × . RECAL CONV_FP Figure 31. Example of Full Power Mode Proximity Detection with Forced Recalibration (FP_PROXIMITY_CNT = 1 and FP_PROXIMITY_RECAL = 40) ...

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... Table 13 shows how FF_SKIP_CNT controls the update rate of the fast FIFO. The recommended value for the setting when using all 12 conversion stages on the AD7147A is 0000 samples skipped. FAST FIFO Update Rate Decimation = 128 1.536 × ...

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... AD7147A 16 CDC STAGEx_FF_WORD0 STAGEx_FF_WORD1 STAGEx_FF_WORD2 STAGEx_FF_WORD3 STAGEx_FF_WORD4 STAGEx_FF_WORD5 STAGEx_FF_WORD6 STAGEx_FF_WORD7 BANK 3 REGISTERS 7 Σ WORD( PROXIMITY SLOW_FILTER_EN COMPARATOR 3 STAGEx_SF_WORD0 |WORD0 – CDC VALUE| STAGEx_SF_WORD1 STAGEx_SF_WORD2 STAGEx_SF_WORD3 SLOW_FILTER_UPDATE_LVL STAGEx_SF_WORD4 REGISTER 0x003 STAGEx_SF_WORD5 STAGEx_SF_WORD6 STAGEx_SF_WORD7 BANK 3 REGISTERS NOTES 1. SLOW_FILTER_EN, WHICH IS THE NAME OF THE OUTPUT OF COMPARATOR 3, IS SET AND SW1 IS CLOSED WHEN |STAGEx_SF_ WORD0 – CDC VALUE | EXCEEDS THE VALUE PROGRAMMED IN THE SLOW_FILTER_UPDATE_LVL REGISTER PROVIDING PROXIMITY IS NOT SET. 2. PROXIMITY 1 IS SET WHEN |STAGEx_FF_ WORD0 – ...

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... STAGEx_OFFSET_HIGH and STAGEx_OFFSET_LOW values, and are based on the threshold sensitivity settings and the ambient value. These values are sufficient to detect a sensor contact and result in the AD7147A asserting the INT output when the threshold levels are exceeded. THRESHOLD EQUATIONS On-Chip Logic Stage High Threshold ...

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... Figure 36. Typical Sensor Behavior with Calibration Applied on the Data Path SLOW FIFO As shown in Figure 33, there are a number of FIFOs imple- mented on the AD7147A. These FIFOs are located in Bank 3 of the on-chip memory. The slow FIFOs are used by the on-chip logic to monitor the ambient capacitance level from each sensor. ...

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... This algorithm continu- ously monitors the output levels of each sensor and automatically rescales the threshold levels in proportion to the sensor area covered by the user result, the AD7147A maintains optimal threshold and sensitivity levels for all users regardless of their finger sizes. ...

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... STAGEx_OFFSET_LOW_CLAMP value. Used in Equation 1. An initial value (based on sensor characterization) is programmed into this register at startup. The AD7147A on-chip calibration algorithm automatically updates this register based on the amount of sensor drift due to changing ambient conditions. Set this register to 80% of the STAGEx_OFFSET_HIGH_CLAMP value. ...

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... The sensor-touch interrupt mode is implemented when the host processor requires an interrupt only when a sensor is contacted. Configuring the AD7147A into this mode results in the interrupt being asserted when the user makes contact with the sensor and again when the user stops touching the sensor. The second interrupt is required to alert the host processor that the user is no longer contacting the sensor ...

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... AD7147A STAGE0 STAGE1 STAGE2 CONVERSIONS INT 1 SERIAL READS NOTES THIS IS AN EXAMPLE OF A CDC CONVERSION-COMPLETE INTERRUPT. THIS TIMING EXAMPLE SHOWS THAT THE INTERRUPT OUTPUT HAS BEEN ENABLED TO BE ASSERTED AT THE END OF A CONVERSION CYCLE FOR STAGE0, STAGE5, AND STAGE9. THE INTERRUPTS FOR ALL OTHER STAGES HAVE BEEN DISABLED. ...

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... Asserted while signal on GPIO pin is low 1 0 Pulses low at low-to-high GPIO transition 0 1 Not triggered 0 1 Pulses low at high-to-low GPIO transition 1 0 Not triggered 1 0 Asserted while signal on GPIO pin is high 0 1 Not triggered Rev Page AD7147A ...

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... AD7147A SERIAL READBACK GPIO INPUT HIGH WHEN REGISTER IS READ BACK GPIO INPUT INT OUTPUT GPIO INPUT LOW WHEN REGISTER IS READ BACK GPIO INPUT INT OUTPUT 1 READ GPIO_INT_STATUS BIT TO RESET INT OUTPUT. Figure 42. Example of INT Output Controlled by the GPIO Input (GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 00) ...

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... Table 16 lists the interrupt output behavior for each of the GPIO configuration setups. USING THE GPIO TO TURN ON/OFF AN LED The GPIO on the AD7147A can be used to turn an LED on and off by setting the GPIO as either output high or low. Setting the GPIO output high turns on the LED; setting the GPIO output low turns off the LED ...

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... The master then supplies the 16-bit input data-word on the SDI line. The AD7147A clocks the data into the register addressed in the command word. If there is more than one word of data to be clocked in, the AD7147A automatically increments the address pointer and clocks the subsequent data-word into the next register ...

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... CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB-JUSTIFIED REGISTER ADDRESS) Reading Data A read transaction begins when the master writes the command word to the AD7147A with the read/write bit set to 1. The master then supplies 16 clock pulses per data-word to be read, and the AD7147A clocks out data from the addressed register on the SDO line ...

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... The AD7147A-1 has a 7-bit device address, Address 0101 1XX. The lower two bits are set by tying the ADD0 and ADD1 pins high or low. The AD7147A-1 responds when the master device sends its device address over the bus. The AD7147A-1 cannot initiate data transfers on the bus. 2 Table 19 ...

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... LSBs of data to be written to the internal register. The AD7147A-1 address pointer register automatically incre- ments after each write. This allows the master to sequentially write to all registers on the AD7147A-1 in the same write transaction. However, the address pointer register does not REGISTER ADDRESS [A15:A8] ...

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... ACK = ACKNOWLEDGE BIT ACK = NO ACKNOWLEDGE BIT 2 Figure 54. Example of Sequential I C Write and Readback Operations This allows the AD7147A to be connected directly to processors whose supply voltage is less than the minimum operating voltage of the AD7147A without the need for external level-shifters and SPI serial The V 1 ...

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... D 1.0 5 CAPACITIVE SENSOR BOARD 5 CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING Figure 56. Capacitive Sensor Board, Side View CAPACITIVE SENSOR BOARD 5 GROUNDED METAL SHIELD CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING Figure 57. Capacitive Sensor Board with Grounded Shield AD7147A Max Unit ...

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... Note that the specific registers required to be read back depend on each application. For buttons, the interrupt status registers are read back while other sensors read data back from the AD7147A according to the slider or wheel algorithm requirements. Analog Devices can provide this information after the user develops the sensor board. ...

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... CC 1μF TO 10μF 100nF (OPTIONAL) Figure 60. Typical Application Circuit with I Rev Page BUTTON BUTTON SCROLL WHEEL BUTTON BUTTON SENSOR PCB CIN5 BUTTON A5 CIN7 BUTTON B5 CIN9 BUTTON C5 D5 2-WAY SWITCH CIN12 E5 PLANE AROUND SENSORS CONNECTED TO AC SHIELD 2 C Interface AD7147A ...

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... Bank 3 registers contain the results of each conversion stage. These registers automatically update at the end of each conversion sequence. Although these registers are primarily used by the AD7147A internal data processing, they are accessible by the host processor for additional external data processing, if desired. Default values are undefined for Bank 2 registers and Bank 3 registers until after power-up and configuration of the Bank 2 registers ...

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... Interrupt polarity control 0 = active low 1 = active high R/W EXT_SOURCE Excitation source control 0 = enable excitation source to CINx pins 1 = disable excitation source to CINx pins Unused Set to 0 R/W CDC_BIAS CDC bias current control 00 = normal operation 01 = normal operation + 20 normal operation + 35 normal operation + 50% Rev Page AD7147A ...

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... AD7147A Table 22. STAGE_CAL_EN Register Default Address Data Bit Value Type 0x001 [0] 0 R/W [1] 0 R/W [2] 0 R/W [3] 0 R/W [4] 0 R/W [5] 0 R/W [6] 0 R/W [7] 0 R/W [8] 0 R/W [9] 0 R/W [10] 0 R/W [11] 0 R/W [13:12] 0 R/W [15:14] 0 R/W Name Description STAGE0_CAL_EN STAGE0 calibration enable 0 = disable 1 = enable STAGE1_CAL_EN STAGE1 calibration enable 0 = disable 1 = enable STAGE2_CAL_EN STAGE2 calibration enable ...

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... PROXIMITY_DETECTION_RATE Proximity detection rate. Value is multiplied determine actual detection rate. SLOW_FILTER_UPDATE_LVL Slow filter update level. Name Description FP_PROXIMITY_RECAL Full power mode proximity recalibration time control LP_PROXIMITY_RECAL Low power mode proximity recalibration time control Rev Page AD7147A ...

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... AD7147A Table 26. STAGE_LOW_INT_ENABLE Register Default Address Data Bit Value Type 0x005 [0] 0 R/W [1] 0 R/W [2] 0 R/W [3] 0 R/W [4] 0 R/W [5] 0 R/W [6] 0 R/W [7] 0 R/W [8] 0 R/W [9] 0 R/W [10] 0 R/W [11] 0 R/W [13:12] 0 R/W [15:14] 0 R/W Name Description STAGE0_LOW_INT_ENABLE STAGE0 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded STAGE1_LOW_INT_ENABLE ...

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... INT asserted if STAGE9 high threshold is exceeded STAGE10_HIGH_INT_ENABLE STAGE10 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE10 high threshold is exceeded STAGE11_HIGH_INT_ENABLE STAGE11 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE11 high threshold is exceeded Unused Set to 0 Rev Page AD7147A ...

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... AD7147A Table 28. STAGE_COMPLETE_INT_ENABLE Register Default Address Data Bit Value Type 0x007 [0] 0 R/W [1] 0 R/W [2] 0 R/W [3] 0 R/W [4] 0 R/W [5] 0 R/W [6] 0 R/W [7] 0 R/W [8] 0 R/W [9] 0 R/W [10] 0 R/W [11] 0 R/W [12] 0 R/W [15:13] Name Description STAGE0_COMPLETE_INT_ENABLE STAGE0 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE0 conversion STAGE1_COMPLETE_INT_ENABLE STAGE1 conversion interrupt control ...

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... STAGE9 CDC conversion low limit interrupt result 1 = indicates STAGE9_LOW_THRESHOLD value was exceeded STAGE10_LOW_INT_STATUS STAGE10 CDC conversion low limit interrupt result 1 = indicates STAGE10_LOW_THRESHOLD value was exceeded STAGE11_LOW_INT_STATUS STAGE11 CDC conversion low limit interrupt result 1 = indicates STAGE11_LOW_THRESHOLD value was exceeded Unused Set to 0 Rev Page AD7147A ...

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... AD7147A Table 30. STAGE_HIGH_INT_STATUS Register Default Address Data Bit Value Type 0x009 [ [ [ [ [ [ [ [ [ [ [10 [11 [15:12] 1 Registers self-clear to 0 after readback if the limits are not exceeded. 1 Name Description ...

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... STAGE5 CDC 16-bit conversion data CDC_RESULT_S6 STAGE6 CDC 16-bit conversion data CDC_RESULT_S7 STAGE7 CDC 16-bit conversion data CDC_RESULT_S8 STAGE8 CDC 16-bit conversion data CDC_RESULT_S9 STAGE9 CDC 16-bit conversion data CDC_RESULT_S10 STAGE10 CDC 16-bit conversion data CDC_RESULT_S11 STAGE11 CDC 16-bit conversion data Rev Page AD7147A ...

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... AD7147A Table 33. Device ID Register Default Address Data Bit Value Type 0x017 [3: [15:4] 147 R Table 34. Proximity Status Register Default Value Address Data Bit Type 0x042 [ [ [ [ [ [ [ [ [ [ [10 [11] ...

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... CIN5 connected to CDC positive input 11 = CIN5 connected to BIAS (connect unused CINx inputs) CIN6 connection setup 00 = CIN6 not connected to CDC inputs 01 = CIN6 connected to CDC negative input 10 = CIN6 connected to CDC positive input 11 = CIN6 connected to BIAS (connect unused CINx inputs) Set to 0 Rev Page AD7147A ...

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... AD7147A Table 36. STAGEx_CONNECTION[12:7] Register Description ( 11) Default Data Bit Value 1 Type Name [1:0] X R/W CIN7_CONNECTION_SETUP [3:2] X R/W CIN8_CONNECTION_SETUP [5:4] X R/W CIN9_CONNECTION_SETUP [7:6] X R/W CIN10_CONNECTION_SETUP [9:8] X R/W CIN11_CONNECTION_SETUP [11:10] X R/W CIN12_CONNECTION_SETUP [13:12] X R/W SE_CONNECTION_SETUP [14] X R/W NEG_AFE_OFFSET_DISABLE [15] X R/W POS_AFE_OFFSET_DISABLE don’t care. Description CIN7 connection setup 00 = CIN7 not connected to CDC inputs 01 = CIN7 connected to CDC negative input ...

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... Positive threshold sensitivity control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% Positive peak detect setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% level, 101 = 90% level Set to 0 Rev Page AD7147A ...

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... AD7147A Table 39. STAGE0 to STAGE12 Configuration Registers 1 Address Data Bit Default Type 0x080 [15:0] X R/W 0x081 [15:0] X R/W 0x082 [15:0] X R/W 0x083 [15:0] X R/W 0x084 [15:0] X R/W 0x085 [15:0] X R/W 0x086 [15:0] X R/W 0x087 [15:0] X R/W 0x088 [15:0] X R/W 0x089 [15:0] X R/W 0x08A [15:0] X R/W 0x08B [15:0] X R/W 0x08C [15:0] X R/W 0x08D [15:0] X R/W 0x08E [15:0] X R/W 0x08F [15:0] X R/W 0x090 [15:0] X R/W 0x091 [15:0] X R/W 0x092 [15:0] X R/W 0x093 [15:0] X R/W 0x094 [15:0] X R/W 0x095 [15:0] X R/W 0x096 [15:0] X R/W 0x097 [15:0] X R/W 0x098 [15:0] X R/W 0x099 [15:0] X R/W 0x09A [15:0] X R/W 0x09B [15:0] X R/W 0x09C [15:0] X R/W 0x09D ...

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... STAGE11_AFE_OFFSET STAGE11 AFE offset control (see Table 37) STAGE11_SENSITIVITY STAGE11 sensitivity control (see Table 38) STAGE11_OFFSET_LOW STAGE11 initial offset low value STAGE11_OFFSET_HIGH STAGE11 initial offset high value STAGE11_OFFSET_HIGH_CLAMP STAGE11 offset high clamp value STAGE11_OFFSET_LOW_CLAMP STAGE11 offset low clamp value Rev Page AD7147A ...

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... AD7147A BANK 3 REGISTERS All address values are expressed in hexadecimal. Table 40. STAGE0 Results Registers Default 1 Address Data Bit Value Type 0x0E0 [15:0] X R/W 0x0E1 [15:0] X R/W 0x0E2 [15:0] X R/W 0x0E3 [15:0] X R/W 0x0E4 [15:0] X R/W 0x0E5 [15:0] X R/W 0x0E6 [15:0] X R/W 0x0E7 [15:0] X R/W 0x0E8 [15:0] X R/W 0x0E9 [15:0] X R/W 0x0EA [15:0] X R/W 0x0EB [15:0] X R/W 0x0EC [15:0] X R/W 0x0ED [15:0] X R/W 0x0EE [15:0] X R/W 0x0EF [15:0] X R/W 0x0F0 [15:0] X R/W 0x0F1 [15:0] X R/W 0x0F2 [15:0] X R/W 0x0F3 [15:0] X R/W 0x0F4 [15:0] X R/W 0x0F5 ...

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... STAGE1_MIN_WORD1 STAGE1 minimum value FIFO WORD1 STAGE1_MIN_WORD2 STAGE1 minimum value FIFO WORD2 STAGE1_MIN_WORD3 STAGE1 minimum value FIFO WORD3 STAGE1_MIN_AVG STAGE1 average minimum FIFO value STAGE1_LOW_THRESHOLD STAGE1 low threshold value STAGE1_MIN_TEMP STAGE1 temporary minimum value Unused Set to 0 Rev Page AD7147A ...

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... AD7147A Table 42. STAGE2 Results Registers Default Address Data Bit Value 1 Type 0x128 [15:0] X R/W 0x129 [15:0] X R/W 0x12A [15:0] X R/W 0x12B [15:0] X R/W 0x12C [15:0] X R/W 0x12D [15:0] X R/W 0x12E [15:0] X R/W 0x12F [15:0] X R/W 0x130 [15:0] X R/W 0x131 [15:0] X R/W 0x132 [15:0] X R/W 0x133 [15:0] X R/W 0x134 [15:0] X R/W 0x135 [15:0] X R/W 0x136 [15:0] X R/W 0x137 [15:0] X R/W 0x138 [15:0] X R/W 0x139 [15:0] X R/W 0x13A [15:0] X R/W 0x13B [15:0] X R/W 0x13C [15:0] X R/W 0x13D [15:0] X R/W 0x13E [15:0] X R/W 0x13F [15:0] X R/W 0x140 [15:0] X R/W 0x141 [15:0] X R/W 0x142 [15:0] X R/W 0x143 [15:0] X R/W 0x144 [15:0] X R/W 0x145 ...

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... STAGE3_MIN_WORD1 STAGE3 minimum value FIFO WORD1 STAGE3_MIN_WORD2 STAGE3 minimum value FIFO WORD2 STAGE3_MIN_WORD3 STAGE3 minimum value FIFO WORD3 STAGE3_MIN_AVG STAGE3 average minimum FIFO value STAGE3_LOW_THRESHOLD STAGE3 low threshold value STAGE3_MIN_TEMP STAGE3 temporary minimum value Unused Set to 0 Rev Page AD7147A ...

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... AD7147A Table 44. STAGE4 Results Registers Default Address Data Bit Value 1 Type 0x170 [15:0] X R/W 0x171 [15:0] X R/W 0x172 [15:0] X R/W 0x173 [15:0] X R/W 0x174 [15:0] X R/W 0x175 [15:0] X R/W 0x176 [15:0] X R/W 0x177 [15:0] X R/W 0x178 [15:0] X R/W 0x179 [15:0] X R/W 0x17A [15:0] X R/W 0x17B [15:0] X R/W 0x17C [15:0] X R/W 0x17D [15:0] X R/W 0x17E [15:0] X R/W 0x17F [15:0] X R/W 0x180 [15:0] X R/W 0x181 [15:0] X R/W 0x182 [15:0] X R/W 0x183 [15:0] X R/W 0x184 [15:0] X R/W 0x185 [15:0] X R/W 0x186 [15:0] X R/W 0x187 [15:0] X R/W 0x188 [15:0] X R/W 0x189 [15:0] X R/W 0x18A [15:0] X R/W 0x18B [15:0] X R/W 0x18C [15:0] X R/W 0x18D ...

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... STAGE5_MIN_WORD1 STAGE5 minimum value FIFO WORD1 STAGE5_MIN_WORD2 STAGE5 minimum value FIFO WORD2 STAGE5_MIN_WORD3 STAGE5 minimum value FIFO WORD3 STAGE5_MIN_AVG STAGE5 average minimum FIFO value STAGE5_LOW_THRESHOLD STAGE5 low threshold value STAGE5_MIN_TEMP STAGE5 temporary minimum value Unused Set to 0 Rev Page AD7147A ...

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... AD7147A Table 46. STAGE6 Results Registers Default Address Data Bit Value 1 Type 0x1B8 [15:0] X R/W 0x1B9 [15:0] X R/W 0x1BA [15:0] X R/W 0x1BB [15:0] X R/W 0x1BC [15:0] X R/W 0x1BD [15:0] X R/W 0x1BE [15:0] X R/W 0x1BF [15:0] X R/W 0x1C0 [15:0] X R/W 0x1C1 [15:0] X R/W 0x1C2 [15:0] X R/W 0x1C3 [15:0] X R/W 0x1C4 [15:0] X R/W 0x1C5 [15:0] X R/W 0x1C6 [15:0] X R/W 0x1C7 [15:0] X R/W 0x1C8 [15:0] X R/W 0x1C9 [15:0] X R/W 0x1CA [15:0] X R/W 0x1CB [15:0] X R/W 0x1CC [15:0] X R/W 0x1CD [15:0] X R/W 0x1CE [15:0] X R/W 0x1CF [15:0] X R/W 0x1D0 [15:0] X R/W 0x1D1 [15:0] X R/W 0x1D2 [15:0] X R/W 0x1D3 [15:0] X R/W 0x1D4 [15:0] X R/W 0x1D5 ...

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... STAGE7_MIN_WORD1 STAGE7 minimum value FIFO WORD1 STAGE7_MIN_WORD2 STAGE7 minimum value FIFO WORD2 STAGE7_MIN_WORD3 STAGE7 minimum value FIFO WORD3 STAGE7_MIN_AVG STAGE7 average minimum FIFO value STAGE7_LOW_THRESHOLD STAGE7 low threshold value STAGE7_MIN_TEMP STAGE7 temporary minimum value Unused Set to 0 Rev Page AD7147A ...

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... AD7147A Table 48. STAGE8 Results Registers Default Address Data Bit Value 1 Type 0x200 [15:0] X R/W 0x201 [15:0] X R/W 0x202 [15:0] X R/W 0x203 [15:0] X R/W 0x204 [15:0] X R/W 0x205 [15:0] X R/W 0x206 [15:0] X R/W 0x207 [15:0] X R/W 0x208 [15:0] X R/W 0x209 [15:0] X R/W 0x20A [15:0] X R/W 0x20B [15:0] X R/W 0x20C [15:0] X R/W 0x20D [15:0] X R/W 0x20E [15:0] X R/W 0x20F [15:0] X R/W 0x210 [15:0] X R/W 0x211 [15:0] X R/W 0x212 [15:0] X R/W 0x213 [15:0] X R/W 0x214 [15:0] X R/W 0x215 [15:0] X R/W 0x216 [15:0] X R/W 0x217 [15:0] X R/W 0x218 [15:0] X R/W 0x219 [15:0] X R/W 0x21A [15:0] X R/W 0x21B [15:0] X R/W 0x21C [15:0] X R/W 0x21D ...

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... STAGE9_MIN_WORD1 STAGE9 minimum value FIFO WORD1 STAGE9_MIN_WORD2 STAGE9 minimum value FIFO WORD2 STAGE9_MIN_WORD3 STAGE9 minimum value FIFO WORD3 STAGE9_MIN_AVG STAGE9 average minimum FIFO value STAGE9_LOW_THRESHOLD STAGE9 low threshold value STAGE9_MIN_TEMP STAGE9 temporary minimum value Unused Set to 0 Rev Page AD7147A ...

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... AD7147A Table 50. STAGE10 Results Registers Default Address Data Bit Value 1 Type 0x248 [15:0] X R/W 0x249 [15:0] X R/W 0x24A [15:0] X R/W 0x24B [15:0] X R/W 0x24C [15:0] X R/W 0x24D [15:0] X R/W 0x24E [15:0] X R/W 0x24F [15:0] X R/W 0x250 [15:0] X R/W 0x251 [15:0] X R/W 0x252 [15:0] X R/W 0x253 [15:0] X R/W 0x254 [15:0] X R/W 0x255 [15:0] X R/W 0x256 [15:0] X R/W 0x257 [15:0] X R/W 0x258 [15:0] X R/W 0x259 [15:0] X R/W 0x25A [15:0] X R/W 0x25B [15:0] X R/W 0x25C [15:0] X R/W 0x25D [15:0] X R/W 0x25E [15:0] X R/W 0x25F [15:0] X R/W 0x260 [15:0] X R/W 0x261 [15:0] X R/W 0x262 [15:0] X R/W 0x263 [15:0] X R/W 0x264 [15:0] X R/W 0x265 ...

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... STAGE11_MIN_WORD1 STAGE11 minimum value FIFO WORD1 STAGE11_MIN_WORD2 STAGE11 minimum value FIFO WORD2 STAGE11_MIN_WORD3 STAGE11 minimum value FIFO WORD3 STAGE11_MIN_AVG STAGE11 average minimum FIFO value STAGE11_LOW_THRESHOLD STAGE11 low threshold value STAGE11_MIN_TEMP STAGE11 temporary minimum value Unused Set to 0 Rev Page AD7147A ...

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... AD7147AACBZ-RL −40°C to +85° AD7147AACBZ500RL7 −40°C to +85° AD7147A-1ACBZ-RL −40°C to +85° AD7147A-1ACBZ500RL7 −40°C to +85°C 1 EVAL-AD7147EBZ 1 EVAL-AD7147-1EBZ RoHS Compliant Part. 2 This package is halide free. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...