AD7147A Analog Devices, AD7147A Datasheet - Page 16

• Manufacturer Part Number: AD7147A
• Manufacturer: Analog Devices

Specifications of AD7147A

• Resolution (bits): 16bit
• # Chan: 13
• Sample Rate: 111SPS
• Interface: I²C/Ser 2-Wire,Ser,SPI
• Analog Input Type: Capacitive
• Ain Range: ± 8 pF (Delta C)
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

AD7147A
CDC CONVERSION SEQUENCE TIME
Table 10. CDC Conversion Times for Full Power Mode
SEQUENCE_STAGE_NUM
0
1
2
3
4
5
6
7
8
9
10
11
The time required for the CDC to complete the measurement of
all 12 stages is defined as the CDC conversion sequence time. The
SEQUENCE_STAGE_NUM and DECIMATION bits determine
the conversion time, as listed in Table 10.
For example, if the device is operated with a decimation rate
of 128 and the SEQUENCE_STAGE_NUM bit is set to 5 for the
conversion of six stages in a sequence, the conversion sequence
time is 9.216 ms.
Full Power Mode CDC Conversion Sequence Time
The full power mode CDC conversion sequence time for all
12 stages is set by configuring the SEQUENCE_STAGE_NUM
and DECIMATION bits as outlined in Table 10.
Figure 26 shows a simplified timing diagram of the full power
mode CDC conversion time. The full power mode CDC con-
version time (t
Low Power Mode CDC Conversion Sequence Time
with Delay
The frequency of each CDC conversion while operating in the
low power automatic wake-up mode is controlled by using the
LP_CONV_DELAY Bits[3:2] located at Address 0x000 in addi-
tion to the registers listed in Table 10. This feature provides some
flexibility for optimizing the trade-off between the conversion time
needed to meet system requirements and the power consumption
of the AD7147A.
CONVERSION
Figure 26. Full Power Mode CDC Conversion Sequence Time
CDC
CONV_FP
CONVERSION
SEQUENCE N
t
CONV_FP
) is set using the values shown in Table 10.
SEQUENCE N + 1
Decimation = 64
0.768
1.536
2.304
3.072
3.84
4.608
5.376
6.144
6.912
7.68
8.448
9.216
CONVERSION
SEQUENCE N + 2
CONVERSION
Rev. B | Page 16 of 68
Decimation = 128
1.536
3.072
4.608
6.144
7.68
9.216
10.752
12.288
13.824
15.36
16.896
18.432
Conversion Time (ms)
For example, maximum power savings is achieved when the
LP_CONV_DELAY bits are set to 11. With a setting of 11,
the AD7147A automatically wakes up, performing a conversion
every 800 ms.
Table 11. LP_CONV_DELAY Settings
LP_CONV_DELAY Bits
00
01
10
11
Figure 27 shows a simplified timing example of the low power
mode CDC conversion time. As shown, the low power mode CDC
conversion time is set by t
CDC CONVERSION RESULTS
Certain high resolution sensors require the host to read back the
CDC conversion results for processing. The registers required
for host processing are located in Bank 3. The host processes the
data read back from these registers using a software algorithm to
determine position information.
In addition to the results registers in Bank 3, the AD7147A
provides the 16-bit CDC output data directly, starting at
Address 0x00B of Bank 1. Reading back the CDC 16-bit
conversion data register allows for customer-specific application
data processing.
CONVERSION
Figure 27. Low Power Mode CDC Conversion Sequence Time
CDC
CONVERSION
SEQUENCE N
t
CONV_FP
t
CONV_FP
CONV_LP
LP_CONV_DELAY
Delay Between Conversions (ms)
200
400
600
800
and the LP_CONV_DELAY bits.
Decimation = 256
3.072
6.144
9.216
12.288
15.36
18.432
21.504
24.576
27.648
30.72
33.792
36.864
SEQUENCE N + 1
CONVERSION