AD7147A Analog Devices, AD7147A Datasheet - Page 29

no-image

AD7147A

Manufacturer Part Number
AD7147A
Description
Manufacturer
Analog Devices
Datasheet

Specifications of AD7147A

Resolution (bits)
16bit
# Chan
13
Sample Rate
111SPS
Interface
I²C/Ser 2-Wire,Ser,SPI
Analog Input Type
Capacitive
Ain Range
± 8 pF (Delta C)
Adc Architecture
Sigma-Delta
Pkg Type
CSP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD7147ACPZ
Manufacturer:
ADI
Quantity:
300
Part Number:
AD7147ACPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7147ACPZ-1
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7147ACPZ-1500
Manufacturer:
ADI
Quantity:
5
Part Number:
AD7147ACPZ-1500
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7147ACPZ-1500RL7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7147ACPZ-500RL7
Manufacturer:
AD
Quantity:
181
Part Number:
AD7147ACPZ-500RL7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
GPIO INT OUTPUT CONTROL
The INT output signal can be controlled by the GPIO pin when
the GPIO is configured as an input. The GPIO is configured as
an input by setting the GPIO_SETUP bits in the interrupt enable
register to 01. See the
section for more information on how to configure the GPIO.
Enable the GPIO interrupt by setting the GPIO_INT_ENABLE
bit in Register 0x007 to 1, or disable the GPIO interrupt by
clearing this bit to 0. The GPIO status bit in the conversion-
complete interrupt status register reflects the status of the GPIO
Table 16. GPIO Interrupt Behavior
GPIO_INPUT_CONFIG
00 = Negative Level Triggered
00 = Negative Level Triggered
01 = Positive Edge Triggered
01 = Positive Edge Triggered
10 = Negative Edge Triggered
10 = Negative Edge Triggered
11 = Positive Level Triggered
11 = Positive Level Triggered
General-Purpose Input/Output (GPIO)
GPIO Pin
1
0
1
0
1
0
1
0
1
0
GPIO_INT_STATUS
0
1
0
1
1
0
Rev. B | Page 29 of 68
interrupt. This bit is set to 1 when the GPIO has triggered INT .
The bit is cleared upon reading the GPIO_INT_STATUS bit if the
condition that caused the interrupt is no longer present.
The GPIO interrupt can be set to trigger on a rising edge, falling
edge, high level, or low level at the GPIO input pin. Table 16 shows
how the settings of the GPIO_INPUT_CONFIG bits in the inter-
rupt enable (STAGE_LOW_INT_ENABLE) register affect the
behavior of INT .
Figure 42 to Figure 45 show how the interrupt output is cleared
upon a read from the GPIO_INT_STATUS bit.
0
0
1
0
INT
1
1
0
1
INT Behavior
Not triggered
Asserted while signal on GPIO pin is low
Pulses low at low-to-high GPIO transition
Not triggered
Pulses low at high-to-low GPIO transition
Not triggered
Asserted while signal on GPIO pin is high
Not triggered
AD7147A

Related parts for AD7147A