AD7147A Analog Devices, AD7147A Datasheet - Page 40

• Manufacturer Part Number: AD7147A
• Manufacturer: Analog Devices

Specifications of AD7147A

• Resolution (bits): 16bit
• # Chan: 13
• Sample Rate: 111SPS
• Interface: I²C/Ser 2-Wire,Ser,SPI
• Analog Input Type: Capacitive
• Ain Range: ± 8 pF (Delta C)
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

AD7147A
REGISTER MAP
The AD7147A address space is divided into three register
banks, referred to as Bank 1, Bank 2, and Bank 3. Figure 61
illustrates the division of these banks.
Bank 1 registers contain control registers, CDC conversion
control registers, interrupt enable registers, interrupt status
registers, CDC 16-bit conversion data registers, device ID
registers, and proximity status registers.
Bank 2 registers contain the configuration registers used to
configure the individual CINx inputs for each conversion stage.
Initialize the Bank 2 configuration registers immediately after
power-up to obtain valid CDC conversion result data.
ADDR 0x7F0
ADDR 0x00B
ADDR 0x000
ADDR 0x001
ADDR 0x005
ADDR 0x008
ADDR 0x017
ADDR 0x018
ADDR 0x042
ADDR 0x043
CDC 16-BIT CONVERSION DATA
PROXIMITY STATUS REGISTER
CALIBRATION AND SETUP
INVALID DO NOT ACCESS
INVALID DO NOT ACCESS
DEVICE ID REGISTER
INTERRUPT ENABLE
INTERRUPT STATUS
BANK 1 REGISTERS
SETUP CONTROL
(12 REGISTERS)
(4 REGISTERS)
(3 REGISTERS)
(3 REGISTERS)
(1 REGISTER)
(1 REGISTER)
(1 REGISTER)
Figure 61. Layout of Bank 1, Bank 2, and Bank 3 Registers
ADDR 0x0A0
ADDR 0x0A8
ADDR 0x0B0
ADDR 0x0B8
ADDR 0x0C0
ADDR 0x0C8
ADDR 0x0D0
ADDR 0x0D8
ADDR 0x080
ADDR 0x088
ADDR 0x090
ADDR 0x098
Rev. B | Page 40 of 68
STAGE10 CONFIGURATION
STAGE11 CONFIGURATION
STAGE0 CONFIGURATION
STAGE1 CONFIGURATION
STAGE2 CONFIGURATION
STAGE3 CONFIGURATION
STAGE4 CONFIGURATION
STAGE5 CONFIGURATION
STAGE6 CONFIGURATION
STAGE7 CONFIGURATION
STAGE8 CONFIGURATION
STAGE9 CONFIGURATION
BANK 2 REGISTERS
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
Bank 3 registers contain the results of each conversion stage.
These registers automatically update at the end of each conversion
sequence. Although these registers are primarily used by the
AD7147A internal data processing, they are accessible by the
host processor for additional external data processing, if
desired.
Default values are undefined for Bank 2 registers and Bank 3
registers until after power-up and configuration of the Bank 2
registers.
ADDR 0x1DC
ADDR 0x14C
ADDR 0x1B8
ADDR 0x26C
ADDR 0x0E0
ADDR 0x104
ADDR 0x128
ADDR 0x170
ADDR 0x194
ADDR 0x200
ADDR 0x224
ADDR 0x248
BANK 3 REGISTERS
STAGE10 RESULTS
STAGE11 RESULTS
STAGE0 RESULTS
STAGE1 RESULTS
STAGE2 RESULTS
STAGE3 RESULTS
STAGE4 RESULTS
STAGE5 RESULTS
STAGE6 RESULTS
STAGE7 RESULTS
STAGE8 RESULTS
STAGE9 RESULTS
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)