AD5625R Analog Devices, AD5625R Datasheet - Page 23

• Manufacturer Part Number: AD5625R
• Manufacturer: Analog Devices

Specifications of AD5625R

• Resolution (bits): 12bit
• Dac Update Rate: 333kSPS
• Dac Settling Time: 3µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser

EXTERNAL REFERENCE
The V
reference if the application requires it. The default condition of
the on-chip reference is off at power-up. All devices can be
operated from a single 2.7 V to 5.5 V supply.
SERIAL INTERFACE
The AD56x5R/AD56x5 have 2-wire I
faces. The AD56x5R/AD56x5 can be connected to an I
a slave device, under the control of a master device. See Figure 3
for a timing diagram of a typical write sequence.
The AD56x5R/AD56x5 support standard (100 kHz), fast
(400 kHz), and high speed (3.4 MHz) data transfer modes.
High speed operation is only available on selected models. See
the Ordering Guide for a full list of models. Support is not
provided for 10-bit addressing and general call addressing.
The AD56x5R/AD56x5 each has a 7-bit slave address. The
10-lead versions of the part have a slave address whose five
MSBs are 00011, and the two LSBs are set by the state of the
ADDR address pin, which determines the state of the A0 and
A1 address bits. The 14-lead versions of the part have a slave
address whose three MSBs are 001, and the four LSBs are set by
the ADDR1 and ADDR2 address pins, which determine the
state of the A0 and A1 and A2 and A3 address bits, respectively.
The facility to make hardwired changes to the ADDR pin allows
the user to incorporate up to three of these devices on one bus,
as outlined in Table 8.
Table 8. ADDR Pin Settings (10-Lead Package)
ADDR Pin Connection
V
NC
GND
The facility to make hardwired changes to the ADDR1 and the
ADDR2 pins allows the user to incorporate up to nine of these
devices on one bus, as outlined in Table 9.
Table 9. ADDR1, ADDR2 Pin Settings (14-Pin Package)
ADDR2 Pin
Connection
V
V
V
NC
NC
NC
GND
GND
GND
DD
DD
DD
DD
REFIN
pin on the AD56x5R allows the use of an external
ADDR1 Pin
Connection
V
NC
GND
V
NC
GND
V
NC
GND
DD
DD
DD
A3
0
0
0
1
1
1
1
1
1
2
C-compatible serial inter-
A1
0
1
1
A2
0
0
0
0
0
0
1
1
1
A1
0
1
1
0
1
1
0
1
1
A0
0
0
1
2
C bus as
A0
0
0
1
0
0
1
0
0
1
Rev. B | Page 23 of 36
AD5625R/AD5645R/AD5665R, AD5625/AD5665
The 2-wire serial bus protocol operates as follows:
1.
2.
3.
WRITE OPERATION
When writing to the AD56x5R/AD56x5, the user must begin
with a start command followed by an address byte (R/ W = 0),
after which the DAC acknowledges that it is prepared to receive
data by pulling SDA low. The AD5665 requires two bytes of
data for the DAC and a command byte that controls various
DAC functions. Three bytes of data must, therefore, be written
to the DAC, the command byte followed by the most significant
data byte and the least significant data byte, as shown in
and
AD56x5R/AD56x5, a stop condition follows.
READ OPERATION
When reading data back from the AD56x5R/AD56x5, the
user begins with a start command followed by an address byte
(R/ W = 1), after which the DAC acknowledges that it is prepared
to transmit data by pulling SDA low. Two bytes of data are then
read from the DAC, which are both acknowledged by the master
as shown in
Figure 58
The master initiates data transfer by establishing a start
condition when a high-to-low transition on the SDA line
occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address. The slave
address corresponding to the transmitted address responds
by pulling SDA low during the ninth clock pulse (this is
termed the acknowledge bit). At this stage, all other devices
on the bus remain idle while the selected device waits for
data to be written to or read from its shift register.
Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high
period of SCL.
When all data bits have been read or written, a stop
condition is established. In write mode, the master pulls
the SDA line high during the 10
stop condition. In read mode, the master issues a no
acknowledge for the ninth clock pulse (that is, the SDA line
remains high). The master brings the SDA line low before
the 10
pulse to establish a stop condition.
th
Figure 59
clock pulse, and then high during the 10
. After these data bytes are acknowledged by the
and
Figure 60
. A stop condition follows.
th
clock pulse to establish a
th
Figure 57
clock