AD5625R Analog Devices, AD5625R Datasheet - Page 9

• Manufacturer Part Number: AD5625R
• Manufacturer: Analog Devices

Specifications of AD5625R

• Resolution (bits): 12bit
• Dac Update Rate: 333kSPS
• Dac Settling Time: 3µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser

Parameter
t
t
t
t
t
1
2
3
4
12
13
14
15
SP
See Figure 3. High speed mode timing specification applies only to the AD5625RBRUZ-2/AD5625RBRUZ-2REEL7 and AD5665RBRUZ-2/AD5665RBRUZ-2REEL7.
C
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC
behavior of the part.
Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or less than 10 ns for high speed mode.
B
4
refers to the capacitance on the bus line.
LDAC*
CLR
SDA
SCL
Test Conditions
Standard mode
Fast mode
High speed mode, C
High speed mode, C
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
Fast mode
High speed mode
*ASYNCHRONOUS LDAC UPDATE MODE.
P
t
7
S
2
t
t
6
2
B
B
= 100 pF
= 400 pF
t
4
t
11
Figure 3. 2-Wire Serial Interface Timing Diagram
Min
10
20
10
10
10
300
300
30
20
20
20
0
0
t
3
t
1
t
12
Rev. B | Page 9 of 36
AD5625R/AD5645R/AD5665R, AD5625/AD5665
t
Max
300
300
40
80
50
10
15
S
t
t
5
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
6
Description
t
LDAC pulse width low
Falling edge of ninth SCL clock pulse of last byte
of a valid write to LDAC falling edge
CLR pulse width low
Pulse width of spike suppressed
FCL
, fall time of SCL signal
t
14
t
8
t
13
P
t
9