AD5625R Analog Devices, AD5625R Datasheet - Page 28

• Manufacturer Part Number: AD5625R
• Manufacturer: Analog Devices

Specifications of AD5625R

• Resolution (bits): 12bit
• Dac Update Rate: 333kSPS
• Dac Settling Time: 3µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser

AD5625R/AD5645R/AD5665R, AD5625/AD5665
Synchronous LDAC
The DAC registers are updated after new data is read in. LDAC
can be permanently low or pulsed.
Asynchronous LDAC
The outputs are not updated at the same time that the input
registers are written to. When LDAC goes low, the DAC
registers are updated with the contents of the input register.
The LDAC register gives the user full flexibility and control over
the hardware LDAC pin (and software LDAC on the 10-lead
parts that do not have the hardware LDAC pin—see
This register allows the user to select which combination of
channels to simultaneously update when the hardware
pin is executed. Setting the LDAC bit register to 0 for a DAC
channel means that the update of this channel is controlled by
the LDAC pin. If this bit is set to 1, this channel synchronously
updates; that is, the DAC register is updated after new data is
read in, regardless of the state of the LDAC pin. The device
effectively sees the LDAC pin as being pulled low. See
for the
useful in applications when the user wants to simultaneously
update select channels while the rest of the channels are
synchronously updating.
Writing to the DAC using Command 110 loads the 4-bit LDAC
register [DB3:DB0]. The default for each channel is 0; that is,
the LDAC pin works normally. Setting the bits to 1 means that
the DAC register is updated, regardless of the state of the LDAC
pin. See
during the
R
0
LDAC register mode of operation. This flexibility is
Figure 67
S
X
LDAC register setup command.
C2
1
COMMAND
for the contents of the input shift register
C1
1
C0
0
A2
A2
DAC ADDRESS
(DON’T CARE)
A1
A1
A0
A0
DB15 DB14 DB13 DB12 DB11 DB10
X
Table 12
X
Table 13
LDAC
Figure 67. LDAC Setup Command
X
Rev. B | Page 28 of 36
).
DON’T CARE
X
X
Table 12. LDAC Register Mode of Operation on the 10-Lead
LFCSP (Load DAC Register)
LDAC Bits
(DB3 to DB0)
0
1
Table 13. LDAC Register Mode of Operation on the 14-Lead
TSSOP (Load DAC Register)
LDAC Bits
(DB3 to DB0)
0
1
X
DB9
X
DB8
X
DB7
LDAC Mode of Operation
Normal operation (default), DAC register
update is controlled by the write command.
The DAC registers are updated after new data
is read in.
LDAC Pin
1/0
x = don’t
care
X
DON’T CARE
DB6
X
DB5
X
DB4
LDAC Operation
Determined by the LDAC pin.
The DAC registers are updated
after new data is read in.
X
DAC D DAC C DAC B DAC A
DB3
(0 = LDAC PIN ENABLED)
DAC SELECT
DB2
DB1
DB0