AD5625R Analog Devices, AD5625R Datasheet - Page 29

• Manufacturer Part Number: AD5625R
• Manufacturer: Analog Devices

Specifications of AD5625R

• Resolution (bits): 12bit
• Dac Update Rate: 333kSPS
• Dac Settling Time: 3µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser

POWER-DOWN MODES
Command 100 is reserved for the power-up/power-down
function. The power-up/power-down modes are programmed
by setting Bit DB5 and Bit DB4. This defines the output state of
the DAC amplifier, as shown in Table 14. Bit DB3 to Bit DB0
determine to which DAC or DACs the power-up/power-down
command is applied. Setting one of these bits to 1 applies the
power-up/power-down state defined by DB5 and DB4 to the
corresponding DAC. If a bit is 0, the state of the DAC is
unchanged. Figure 69 shows the contents of the input shift
register for the power-up/power-down command.
When Bit DB5 and Bit DB4 are set to 0, the part works normally
with its normal power consumption of 1 mA at 5 V. However,
for the three power-down modes, the supply current falls to
480 nA at 5 V. Not only does the supply current fall, but the
output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This allows the
output impedance of the part to be known while the part is in
power-down mode. The outputs can either be connected
internally to GND through a 1 kΩ or 100 kΩ resistor or be left
open-circuited (three-state) as shown in Figure 66.
Note that the 14-lead TSSOP models offer the power-down
function when the part is operated with a V
The 10-lead LFCSP models offer the power-down function
when the part is powered with a V
R
0
S
X
C2
1
COMMAND
C1
0
C0
0
A2
A2
DAC ADDRESS
(DON’T CARE)
DD
A1
A1
of 2.7 V to 5.5 V.
A0
A0
DD
of 3.6 V to 5.5 V.
DB15 DB14 DB13 DB12 DB11 DB10
X
Figure 69. Power-Up/Power-Down Command
X
X
Rev. B | Page 29 of 36
DON’T CARE
AD5625R/AD5645R/AD5665R, AD5625/AD5665
X
X
Table 14. Modes of Operation for the AD56x5R/AD56x5
DB5
0
0
1
1
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down. The time to exit power-
down is typically 4 μs for V
X
DB9
X
STRING DAC
RESISTOR
DB4
0
1
0
1
DB8
X
Figure 68. Output Stage During Power-Down
DON’T CARE
DB7
X
DB6
Operating Mode
Normal operation
Power-down modes
1 kΩ pull-down resistor to GND
100 kΩ pull-down resistor to GND
Three-state, high impedance
X
POWER-DOWN
AMPLIFIER
CIRCUITRY
DOWN MODE
DD
DB5
PD1
POWER-
= 5 V or V
DB4
PD0
DAC D DAC C DAC B DAC A
DB3
(1 = DAC SELECTED)
DD
NETWORK
RESISTOR
DAC SELECT
= 3 V.
DB2
DB1
V
OUT
DB0