AD5625R Analog Devices, AD5625R Datasheet - Page 32
AD5625R
Manufacturer Part Number
AD5625R
Description
Manufacturer
Analog Devices
Datasheet
1.AD5625.pdf
(36 pages)
Specifications of AD5625R
Resolution (bits)
12bit
Dac Update Rate
333kSPS
Dac Settling Time
3µs
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Voltage Out
Dac Input Format
I2C/Ser 2-wire,Ser
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AD5625R/AD5645R/AD5665R, AD5625/AD5665
OUTLINE DIMENSIONS
PIN 1 INDEX
SEATING
PLANE
COPLANARITY
AREA
0.80
0.75
0.70
1.05
1.00
0.80
PIN 1
4.50
4.40
4.30
0.10
0.15
0.05
* FOR PROPER CONNECTION OF THE EXPOSED PAD PLEASE REFER TO
Figure 74. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION
OF THIS DATA SHEET.
Figure 75. 14-Lead Thin Shrink Small Outline Package [TSSOP]
14
1
0.65 BSC
0.30
0.19
TOP VIEW
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
BSC SQ
3.00
5.10
5.00
4.90
3 mm × 3 mm Body, Very Very Thin, Dual Lead
0.80 MAX
0.55 NOM
Dimensions shown in millimeters
Dimensions shown in millimeters
8
7
6.40
BSC
Rev. B | Page 32 of 36
SEATING
PLANE
1.20
MAX
0.20 REF
(CP-10-9)
(RU-14)
0.50
0.40
0.30
0.05 MAX
0.02 NOM
0.20
0.09
0.30
0.23
0.18
6
5
(BOTTOM VIEW)
8°
0°
* EXPOSED
2.48
2.38
2.23
PAD
1
10
0.50 BSC
1.74
1.64
1.49
0.75
0.60
0.45