ADP5022 Analog Devices, ADP5022 Datasheet - Page 20

• Manufacturer Part Number: ADP5022
• Description: Dual 3 MHz, 600 mA Buck Regulator with 150 mA LDO
• Manufacturer: Analog Devices

ADP5022
The peak-to-peak output voltage ripple for the selected output
capacitor and inductor values is calculated using the following
equation:
Capacitors with lower equivalent series resistance (ESR) are
preferred to guarantee low output voltage ripple, as shown in
the following equation:
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 7 μF and a
maximum of 40 μF.
Table 8. Suggested 10 μF Capacitors
Vendor
Murata
Taiyo Yuden
TDK
Panasonic
The buck regulators require 10 μF output capacitors to guar-
antee stability and response to rapid load variations and to
transition in and out the PWM/PSM modes. In certain
applications, where one or both buck regulator powers a
processor, the operating state is known because it is con-
trolled by software. In this condition, the processor can drive
the MODE pin according to the operating state; consequently, it
is possible to reduce the output capacitor from 10 μF to 4.7 μF
because the regulator does not expect a large load variation
when working in PSM mode, see Figure 50.
2.5V TO 5.5V
Figure 50. Processor System Power Management with PSM/PWM Control
V
V
ESR
IN
RIPPLE
COUT
=
C2
4.7µF
≤
(
2
Type
X5R
X5R
X5R
X5R
V
π
I
C3
4.7µF
C1
1µF
RIPPLE
VDDA
RIPPLE
×
VIN1
VIN2
VIN3
EN1
EN2
EN3
f
SW
MICRO PMU
ADP5022
)
Model
GRM188R60J106
JMK107BJ475
C1608JB0J106K
ECJ1VB0J106M
V
×
IN
2
×
L
×
C
SW1
VOUT1
PGND1
MODE
SW2
VOUT2
PGND2
VOUT3
OUT
1µH
1µH
L1
L2
=
8
×
Case
Size
0603
0603
0603
0603
f
I
SW
C4
4.7µF
C5
4.7µF
C6
1µF
RIPPLE
×
C
SUB-SYSTEM
PROCESSOR
VCORE
GPIO
VIO
VANA
Voltage
Rating (V)
6.3
6.3
6.3
6.3
OUT
ANALOG
Rev. C | Page 20 of 28
Input Capacitor
Higher value input capacitors help to reduce the input voltage
ripple and improve transient response. Maximum input capa-
citor current is calculated using the following equation:
To minimize supply noise, place the input capacitor as close
to the VIN pin of the BUCK as possible. As with the output
capacitor, a low ESR capacitor is recommended.
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 3 μF and a
maximum of 10 μF. A list of suggested capacitors is shown in
Table 9.
Table 9. Suggested 4.7 μF Capacitors
Vendor
Murata
Taiyo Yuden
Panasonic
LDO CAPACITOR SELECTION
Output Capacitor
The ADP5022 LDO is designed for operation with small, space-
saving ceramic capacitors but functions with most commonly
used capacitors as long as care is taken with the ESR value. The
ESR of the output capacitor affects stability of the LDO control
loop. A minimum of 0.70 μF capacitance with an ESR of 1 Ω
or less is recommended to ensure stability of the ADP5022.
Transient response to changes in load current is also affected
by output capacitance. Using a larger value of output capacit-
ance improves the transient response of the ADP5022 to large
changes in load current.
Input Bypass Capacitor
Connecting a 1 μF capacitor from VIN3 to GND reduces
the circuit sensitivity to printed circuit board (PCB) layout,
especially when long input traces or high source impedance
are encountered. If greater than 1 μF of output capacitance is
required, increase the input capacitor to match it.
Table 10. Suggested 1.0 μF Capacitors
Vendor
Murata
TDK
Panasonic
Taiyo Yuden
I
CIN
≥
I
LOAD
Type
X5R
X5R
X5R
Type
X5R
X5R
X5R
X5R
(
MAX
)
Model
GRM188R60J475ME19D
JMK107BJ475
ECJ-0EB0J475M
V
Model
GRM155B30J105K
C1005JB0J105KT
ECJ0EB0J105K
LMK105BJ105MV-F
OUT
(
V
V
IN
IN
−
V
OUT
)
Case
Size
0402
0402
0402
0402
Case
Size
0603
0603
0402
Voltage
Rating (V)
6.3
6.3
6.3
10.0
Voltage
Rating
(V)
6.3
6.3
6.3