ADP5040

... VOUT1 L1 1µ OUT1 1.2A FB1 10µF PGND FPWM MODE PSM/PWM VOUT2 V AT OUT2 300mA FB2 C2 R3 2.2µF R4 VOUT3 V AT OUT3 300mA FB3 C4 R7 2.2µF R3 ©2011 Analog Devices, Inc. All rights reserved. ADP5040 ADP5040 www.analog.com ...

... ADP5040 TABLE OF CONTENTS Features .............................................................................................. 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 General Specifications ................................................................. 3 Buck Specifications ....................................................................... 3 LDO1, LDO2 Specifications ....................................................... 4 Input and Output Capacitor, Recommended Specifications .. 5 Absolute Maximum Ratings ............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Theory of Operation ...................................................................... 25 REVISION HISTORY 12/11— ...

... VOUT1, VOUT2, and VOUT3 reache 90% of their = −40°C to +125°C for minimum/maximum J 1 Min Typ 2.3 −3 −0.05 −0.1 0.485 0.5 100 21 0.2 ADP5040 Max Unit 2.275 V 3 µA °C °C µs µ µA Max Unit 5 ...

... ADP5040 Parameter Symbol SW CHARACTERISTICS SW On Resistance R R Current Limit I ACTIVE PULL-DOWN OSCILLATOR FREQUENCY F 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). LDO1, LDO2 SPECIFICATIONS 0 1.7 V (whichever is greater) to 5.5V; AVIN, VIN1 ≥ VIN2, VIN3; C ...

... T = −40°C to +125°C MIN1 −40°C to +125°C MIN2 −40°C to +125°C MIN34 −40°C to +125°C ESR J Rev Page ADP5040 Min Typ Max Unit Min Typ Max Unit 4.7 40 µ µF 0.70 µ ...

... ADP5040 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter AVIN to AGND VIN1 to AVIN PGND to AGDN VIN2, VIN3, VOUTx, ENx, MODE, FBx AGND SW to PGND Storage Temperature Range Operating Junction Temperature Range Soldering Conditions ESD Human Body Model ESD Charged Device Model ESD Machine Model Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device ...

... Exposed Pad. ( AGND = Analog Ground). The exposed pad must be connected to the system ground plane. ADP5040 TOP VIEW (Not to Scale) FB3 1 15 FB2 VOUT3 2 14 VOUT2 VIN3 3 13 VIN2 4 12 FB1 EN3 VOUT1 NOTES 1. EXPOSED PAD MUST BE CONNECTED TO SYSTEM GROUND PLANE. Figure 2. Pin Configuration—View from Top of the Die Rev Page ADP5040 ...

... ADP5040 TYPICAL PERFORMANCE CHARACTERISTICS VIN1 = VIN2 = VIN3 = AVIN = 5 OUT1 2 V OUT2 3 V OUT3 4 2.0V/DIV 1MΩ B CH4 500M A CH2 W 2.0V/DIV 1MΩ B CH2 20.0M W 2.0V/DIV 1MΩ B CH3 500M W Figure 3. 3-Channel Start-Up Waveforms V OUT3 4 V OUT2 2 V OUT1 1MΩ B 2.0V/DIV 20.0M CH1 A CH1 W 1MΩ ...

... Figure 13. Buck Load Regulation Across Temperature 3.3 V, OUT1 3.32 –40°C +25°C 3.31 +85°C 3.30 3.29 3.28 3.27 3.26 3.25 0.01 1 Figure 14. Buck Load Regulation Across Temperature 1.8 V, OUT1 Rev Page ADP5040 –40°C +25°C +85°C 0.1 1 OUTPUT CURRENT (A) = 1.2 V, OUT1 Auto Mode –40°C +25°C +85°C 0.1 1 OUTPUT CURRENT (A) = 3.8 V, OUT1 PWM Mode –40°C +25° ...

... ADP5040 1.820 1.815 1.810 1.805 1.800 1.795 1.790 1.785 1.780 0.01 0.1 OUTPUT CURRENT (A) Figure 15. Buck Load Regulation Across Temperature 1.8 V, PWM Mode OUT1 1.205 1.200 1.195 1.190 1.185 1.180 0.01 0.1 OUTPUT CURRENT (A) Figure 16. Buck Load Regulation Across Temperature 1.2 V, PWM Mode OUT1 100 ...

... OUT1 0.0001 0.001 0.01 0.1 OUTPUT CURRENT ( 5 3.3 V, Auto Mode IN OUT1 0.001 0.01 0.1 OUTPUT CURRENT ( 5 3.3 V, PWM Mode IN OUT1 ADP5040 –40°C +25°C +85°C 1 –40°C +25°C +85°C 1 ...

... ADP5040 100 0.0001 0.001 0.01 OUTPUT CURRENT (A) Figure 27. Buck Efficiency vs. Load Current, Across Temperature 5 1.8 V, Auto Mode IN OUT1 100 0.001 0.01 0.1 OUTPUT CURRENT (A) Figure 28. Buck Efficiency vs. Load Current, Across Temperature 5 1.8 V, PWM Mode ...

... CH3 3.0V/DIV 20.0M W 40.0mV/DIV 20.0M CH4 = 1 mA, Auto Mode OUT1 OUT1 V OUT 200mA/DIV 1MΩ B CH2 20.0M A CH1 640mV W 1MΩ B CH3 3.0V/DIV 20.0M W CH4 10.0mV/DIV 20. mA, PWM Mode OUT1 OUT1 ADP5040 5µs/DIV 500MS/s 2.0ns/pt 5µs/DIV 500MS/s 2.0ns/pt 200ns/DIV 500MS/s 2.0ns/pt ...

... ADP5040 V OUT 200mA/DIV 1MΩ B CH2 20.0M A CH1 W 1MΩ B CH3 3.0V/DIV 20.0M W CH4 20.0mV/DIV 20.0M Figure 39. Typical Waveforms 1 OUT1 OUT1 V OUT 200mA/DIV 1MΩ B CH2 20.0M A CH3 W 1MΩ B CH3 3.0V/DIV 20.0M W 40.0mV/DIV 20.0M CH4 Figure 40. Typical Waveforms 1 OUT1 OUT1 ...

... V, Auto Mode OUT1 SW V OUT I OUT 1MΩ B CH1 4.0V/DIV 20.0M A CH3 150mA W B CH2 100mV/DIV 20.0M W 1MΩ B 300mA/DIV 20.0M CH3 500 mA, OUT1 V = 1.8 V, Auto Mode OUT1 ADP5040 500µs/DIV 20.0MS/s 50.0ns/pt 500µs/DIV 20.0MS/s 50.0ns/pt 500µs/DIV 20.0MS/s 50.0ns/pt ...

... ADP5040 OUT 2 I OUT 3 1MΩ B 4.0V/DIV 20.0M CH1 A CH3 W B CH2 50.0mV/DIV 20.0M W 1MΩ B 120M CH3 100mA/DIV W Figure 51. Buck Response to Load Transient 1.2 V, Auto Mode OUT1 OUT 2 I OUT 3 B CH1 4.0V/DIV 20.0M A CH3 W B CH2 50.0mV/DIV 20.0M W 1MΩ B CH3 ...

... OUT OUT EN 1MΩ B CH1 2.0V/DIV 20.0M A CH1 1.72V W 1MΩ B CH2 1.0V/DIV 20. CH3 200mA/DIV 20.0M W Figure 62. LDO1, LDO2 Startup 1 OUT ADP5040 50.0µs/DIV 200MS/s 5.0ns/ OUT 50.0µs/DIV 200MS/s 5.0ns/ OUT 50.0µs/DIV 200MS/s 5.0ns/ OUT ...

... ADP5040 4.758 4.708 4.658 4.608 0.001 0.01 OUTPUT CURRENT (A) Figure 63. LDO1, LDO2 Load Regulation Across Input Voltage, V 3.40 3.38 3.36 3.34 3.32 3.30 3.28 3.26 3.24 3.22 3.20 0.001 0.01 OUTPUT CURRENT (A) Figure 64. LDO1, LDO2 Load Regulation Across Input Voltage, V 1.800 1.795 1.790 1.785 1.780 1.775 1.770 0.001 0.01 OUTPUT CURRENT (A) Figure 65. LDO1, LDO2 Load Regulation Across Input Voltage ...

... Figure 73. LDO1, LDO2 Line Regulation Across Input Voltage, V OUT 200 180 160 140 120 100 5.1 5 3.3 V Figure 74. LDO1, LDO2 Ground Current vs. Output Current, V OUT Rev Page ADP5040 100µA 1mA 10mA 100mA 200mA 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 100µA 1mA 10mA 100mA 200mA 3.0 3.5 4.0 4 ...

... ADP5040 200 180 160 140 120 100 3.8 4.3 4.8 INPUT VOLTAGE (V) Figure 75. LDO1, LDO2 Ground Current vs. Input Voltage, Across Output Load (A 3.3 V OUT V OUT 2 I OUT 3 B CH2 30.0mV/DIV 20.0M A CH3 W 1MΩ B CH3 20.0M 80.0mA/DIV W Figure 76. LDO1, LDO2 Response to Load Transient mA ...

... A CH3 4.86V W 1MΩ B CH3 1.0V/DIV 20. 1.8 V OUT OUT B CH2 20.0mV/DIV 20.0M A CH3 4.48V W 1MΩ B CH3 1.0V/DIV 20. 1.2 V OUT ADP5040 200µs/DIV 1.0MS/s 1.0µs/pt 500µs/DIV 1.0MS/s 1.0µs/pt 200µs/DIV 1.0MS/s 1.0µs/pt ...

... ADP5040 OUT CH2 20.0mV/DIV 20.0M A CH3 W 1MΩ B CH3 1.0V/DIV 20.0M W Figure 87. LDO1, LDO2 Response to Line Transient, Input Voltage from 3 3 1.8 V OUT OUT CH2 20.0mV/DIV 20.0M A CH3 W 1MΩ B CH3 1.0V/DIV 20.0M W Figure 88. LDO1, LDO2 Response to Line Transient, Input Voltage from 3 ...

... Rev Page ADP5040 1mA 10mA 100mA 200mA 300mA 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 96. LDO2 PSRR Across Output Load 3 2.8 V IN3 OUT3 1mA 10mA 100mA ...

... ADP5040 –10 1mA 10mA –20 100mA 200mA –30 300mA –40 –50 –60 –70 –80 –90 –100 10 100 1k 10k 100k FREQUENCY (Hz) Figure 99. LDO1 PSRR Across Output Load 5 1.5 V IN2 OUT2 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 10 1M 10M Rev ...

... This operating mode reduces the switching and quiescent current losses. Rev Page ENBK ENABLE & MODE CONTROL MODE SEL OPMODE_FUSES ENLDO2 LDO2 VDDA CONTROL ENLDO1 VIN3 ADP5040 MODE EN1 EN2 EN3 600Ω FB3 VOUT3 ...

... Undervoltage Lockout To protect against battery discharge, undervoltage lockout (UVLO) circuitry is integrated in the ADP5040. If the input voltage on AVIN drops below a typical 2.15 V UVLO threshold, all channels shut down. In the buck channel, both the power switch and the synchronous rectifier turn off. When the voltage on AVIN rises above the UVLO threshold, the part is enabled once more ...

... LDO2 is optimized to supply analog circuits because it offers better noise performance compared to LDO1. LDO1 should be used in applications where noise performance is not critical. Rev Page ADP5040 and V are internally set to 0.5 V. The FB3 VOUT2, VOUT3 ...

... NO POWER APPLIED TO AVIN. ALL REGULATORS TURNED OFF NO POWER AVIN > VUVLO AVIN < VUVLO POR INTERNAL CIRCUIT BIASED REGULATORS NOT ACTIVATED END OF POR STANDBY ALL ENx = LOW ENx = HIGH ACTIVE ALL REGULATORS ACTIVATED Figure 104. ADP5040 State Flow Rev Page Data Sheet AVIN < VUVLO ...

... The peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation RIPPLE Rev Page ADP5040 × (1 − TEMPCO) × (1 − TOL) OUT BIAS VOLTAGE (V) Figure 105. Typical Capacitor Performance ...

... Referring to Figure 103 the maximum value not to exceed 200 kΩ. Output Capacitor The ADP5040 space-saving ceramic capacitors, but they function with most commonly used capacitors as long as care is taken with the ESR value. The ESR of the output capacitor affects stability of the LDO control loop. A minimum of 0.70 µ ...

... LDO over 0402 10.0 temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP5040 imperative that the effects of dc bias, temperature, and tolerances on the ADP5040 as behavior of the capacitors be evaluated for each application. POWER DISSIPATION/THERMAL CONSIDERATIONS ...

... V (4) ground). The amount of transition loss is calculated by: P where t switching node, SW. For the ADP5040, the rise and fall times of SW are in the order of 5 ns. If the preceding equations and parameters are used for (5) estimating the converter efficiency, note that the equations do not describe all of the converter losses, and the parameter values given are typical numbers ...

... D , can be estimated using Equation 14. J ADP5040 (Equation 14) is less than 125°C. Handbook, which is available L1 1µ OUT1 1. 10µF FPWM PWM/PSM V AT OUT2 300mA C5 2.2µ OUT3 300mA C6 2.2µ ADP5040 (15) power ...

... See Figure 109 for an example layout. 2.5 3.0 3.5 4.0 4.5 5.0 VOUT3 – 1µF 10V/XR5 0402 AVIN VIN AGND PGND ADP5040 EN1 C2 – 1µF 10V/XR5 0402 VOUT2 Figure 109. Evaluation Board Layout Rev Page 5.5 6.0 6.5 7.0 mm C4– 2.2µF 6.3V/XR5 0402 ...

... IC1 3-regulator micro PMU Part Number Vendor JMK107BJ475 Taiyo-Yuden LMK105BJ105MV-F Taiyo-Yuden JMK107BJ106MA-T Taiyo-Yuden JMK105BJ225MV-F Taiyo-Yuden LQM2MPN1R0NG0B Murata MDT2520-CN Toko XPL2010-1102ML Coilcraft ADP5040 Analog Devices Rev Page ADP5040 Package 0603 0402 0603 0402 2.0 × 1.6 × 0.9 (mm) 2.5 × 2.0 × 1.2 (mm) 1.9 × 2.0 × 1.0 (mm) 20-Lead LFCSP ...

... ADP5040 FACTORY PROGRAMMABLE OPTIONS Table 14. Regulator Output Discharge Resistor Options Selection 0 1 Table 15. Under Voltage Lockout options Selection 0 1 All discharge resistors disabled All discharge resistors enabled Min Typ 1.95 2.15 3.10 3.65 Rev Page Data Sheet Max Unit 2.275 V 3.90 V ...

... Dimensions shown in millimeters Temperature Range T = −40°C to +125°C J Rev Page 2.65 PAD 2. 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Description 20-Lead LFCSP_WQ Evaluation Board ADP5040 Package Option CP-20-10 ...

... ADP5040 NOTES Rev Page Data Sheet ...

... Data Sheet NOTES Rev Page ADP5040 ...

... ADP5040 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D096665-0-12/11(0) Rev Page Data Sheet ...