ADP5040 Analog Devices, ADP5040 Datasheet - Page 34

• Manufacturer Part Number: ADP5040
• Description: Micro PMU with 1.2 A Buck Regulator and Two 300 mA LDOs
• Manufacturer: Analog Devices

ADP5040
PCB LAYOUT GUIDELINES
Poor layout can affect
magnetic interference (EMI) and electromagnetic compatibility
(EMC) problems, ground bounce, and voltage losses. Poor
layout can also affect regulation and stability. A good layout is
implemented using the following guidelines:
•
•
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.
Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
mm
VOUT1
0.5
L1 – 1µH
0603
1.0
R
0402
30Ω
FILT
ADP5040
C6 – 10µF
6.3V/XR5
0603
1.5
G P L
P P L
10V/XR5 0603
performance, causing electro-
G P L
C5 – 4.7µF
2.0
P P L
2.5
P P L
3.0
PGND
AVIN
EN1
VIN
SW
Figure 109. Evaluation Board Layout
3.5
Rev. 0 | Page 34 of 40
4.0
C3 – 1µF
10V/XR5
C2 – 1µF
10V/XR5
0402
0402
G P L
G P L
4.5
ADP5040
AGND
•
•
SUGGESTED LAYOUT
See Figure 109 for an example layout.
P P L
P P L
5.0
Maximize the size of ground metal on the component side
to help with thermal dissipation.
Use a ground plane with several vias connecting to the
component side ground to further reduce noise interference
on sensitive circuit nodes.
VOUT3
VOUT2
G P L
G P L
5.5
C5 – 2.2µF
6.3V/XR5
C4– 2.2µF
6.3V/XR5
0402
0402
6.0
6.5
MODE
EN
NC
NC
NC
2
7.0
VIAS LEGEND:
PPL = POWER PLANE (+4V)
GPL = GROUND PLANE
mm
TOP LAYER
2ND LAYER
Data Sheet