ADP5040 Analog Devices, ADP5040 Datasheet - Page 32

• Manufacturer Part Number: ADP5040
• Description: Micro PMU with 1.2 A Buck Regulator and Two 300 mA LDOs
• Manufacturer: Analog Devices

ADP5040
to derive the power lost in the inductor, and then calculate the
power dissipation in the buck converter using Equation 3. Add
the power dissipated in the buck and in the LDOs to find the
total dissipated power.
Note that the buck efficiency curves are typical values and may
not be provided for all possible combinations of V
I
safety margin when calculating the power dissipated in the buck.
A third way to estimate the power dissipation is analytical and
involves modeling the losses in the buck circuit provided by
Equation 8 to Equation 11 and the losses in the LDOs provided
by Equation 12.
Buck Regulator Power Dissipation
The power loss of the buck regulator is approximated by
where:
P
P
The inductor losses are external to the device and they do not
have any effect on the die temperature.
The inductor losses are estimated (without core losses) by
where:
DCR
I
where r is the normalized inductor ripple current.
where:
L is inductance.
F
D is duty cycle.
The
includes the power switch conductive losses, the switch losses,
and the transition losses of each channel. There are other
sources of loss, but these are generally less significant at high
output load currents, where the thermal limit of the application
is. Equation 8 shows the calculation made to estimate the power
dissipation in the buck regulator.
OUT
OUT1(RMS)
DBUCK
L
SW
is the inductor power losses.
. To account for these variations, it is necessary to include a
is switching frequency.
ADP5040
P
R ≈ V
D = V
P
L
P
I
LOSS
is the inductor series resistance.
OUT1
DBUCK
L
is the power dissipation on the
≅
is the rms load current of the buck regulator.
= P
I
(
OUT1
RMS
OUT1
OUT1
= P
DBUCK
)
/V
× (1 − D)/(I
buck regulator power dissipation, P
(
COND
=
RMS
IN1
I
OUT1
+ P
)
2
+ P
×
L
DCR
×
SW
+ P
1
OUT1
+
L
r
TRAN
/12
× L × f
SW
ADP5040
)
buck regulator.
IN
DBUCK
, V
OUT
,
, and
Rev. 0 | Page 32 of 40
(3)
(4)
(5)
(6)
(7)
(8)
The power switch conductive losses are due to the output current,
I
switches that have internal resistance, R
amount of conductive power loss is found by:
For the ADP5040, at 125°C junction temperature and V
3.6 V, R
0.16 Ω. At V
respectively, and at V
0.14 Ω, respectively.
Switching losses are associated with the current drawn by the
driver to turn on and turn off the power devices at the switching
frequency. The amount of switching power loss is given by:
where:
C
C
For the ADP5040, the total of (C
150 pF.
The transition losses occur because the PMOSFET cannot be
turned on or off instantaneously, and the SW node takes some
time to slew from near ground to near V
ground). The amount of transition loss is calculated by:
where t
switching node, SW. For the ADP5040, the rise and fall times of
SW are in the order of 5 ns.
If the preceding equations and parameters are used for
estimating the converter efficiency, note that the equations do
not describe all of the converter losses, and the parameter
values given are typical numbers. The converter performance
also depends on the choice of passive components and board
layout; therefore, a sufficient safety margin should be included
in the estimate.
LDO Regulator Power Dissipation
The power loss of a LDO regulator is given by:
where:
I
V
respectively.
I
Power dissipation due to the ground current is small and it
can be ignored.
The total power dissipation in the
OUT1
LOAD
GND
GATE-P
GATE-N
IN
and V
, flowing through the PMOSFET and the NMOSFET power
is the ground current of the LDO regulator.
P
P
P
P
P
is the load current of the LDO regulator.
COND
SW
TRAN
DLDO
D
is the PMOSFET gate capacitance.
DSON-P
is the NMOSFET gate capacitance.
RISE
= {[P
= (C
OUT
= V
= [(V
= [R
and t
IN1
is approximately 0.2 Ω, and R
DBUCK
GATE-P
are input and output voltages of the LDO,
IN1
= 2.3 V, these values change to 0.31 Ω and 0.21 Ω,
DSON-P
FALL
IN
× I
– V
+ P
+ C
are the rise time and the fall time of the
OUT1
× D + R
IN1
OUT
DLDO1
GATE-N
× (t
= 5.5 V, the values are 0.16 Ω and
) × I
+ P
) × V
RISE
DSON-N
LOAD
DLDO2
GATE-P
+ t
IN1
] + (V
FALL
ADP5040
× (1 – D)] × I
]}
2
+ C
× f
) × f
IN
SW
GATE-N
DSON-P
OUT1
DSON-N
× I
SW
GND
) is approximately
simplifies to:
(and from V
and R
is approximately
Data Sheet
)
OUT1
DSON-N
2
IN1
. The
OUT1
=
(10)
(11)
(12)
(13)
(9)
to