LPC1777FBD208 NXP Semiconductors, LPC1777FBD208 Datasheet - Page 50

• Manufacturer Part Number: LPC1777FBD208
• Description: The LPC1777 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC178X_7X
Objective data sheet
7.15.1.1 Features
7.15.2.1 Features
7.15.1 USB device controller
7.15.2 USB host controller
7.15 USB interface
Remark: The USB Device/Host/OTG controller is available on parts LPC1788/87/86/85
and LPC1778/77/76. The USB Device-only controller is available on parts LPC1774.
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
Details on typical USB interfacing solutions can be found in
The device controller enables 12 Mbit/s data exchange with a USB host controller. It
consists of a register interface, serial interface engine, endpoint buffer memory, and a
DMA controller. The serial interface engine decodes the USB data stream and writes data
to the appropriate endpoint buffer. The status of a completed USB transfer or error
condition is indicated via status registers. An interrupt is also generated if enabled. When
enabled, the DMA controller transfers data between the endpoint buffer and the USB
RAM.
The host controller enables full- and low-speed data exchange with USB devices attached
to the bus. It consists of register interface, serial interface engine and DMA controller. The
register interface complies with the Open Host Controller Interface (OHCI) specification.
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– Attachment of external PHY chip through standard MII or RMII interface.
– PHY register access is available via the MIIM interface.
Fully compliant with USB 2.0 Specification (full speed).
Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.
Supports Control, Bulk, Interrupt and Isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
Supports SoftConnect and GoodLink features.
While USB is in the Suspend mode, the LPC178x/7x can enter one of the reduced
power modes and wake up on USB activity.
Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints.
Allows dynamic switching between CPU-controlled and DMA modes.
Double buffer implementation for Bulk and Isochronous endpoints.
OHCI compliant
Two downstream ports
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 27 December 2011
32-bit ARM Cortex-M3 microcontroller
Section
LPC178x/7x
14.1.
© NXP B.V. 2011. All rights reserved.
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