LPC1777FBD208 NXP Semiconductors, LPC1777FBD208 Datasheet - Page 82

• Manufacturer Part Number: LPC1777FBD208
• Description: The LPC1777 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 17.
C
[1]
[2]
[3]
[4]
[5]
[6]
LPC178X_7X
Objective data sheet
Symbol
t
t
t
BLSLBLSH
BLSHEOW
BLSHDNV
Fig 15. External static memory read/write access (PB = 0)
L
= 30 pF, T
Parameters are shown as RD
Parameters specified for 40 % of V
T
Latest of address valid, EMC_CSx LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1).
After End Of Read (EOR): Earliest of EMC_CSx HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid.
End Of Write (EOW): Earliest of address invalid, EMC_CSx HIGH, EMC_BLSx HIGH (PB = 1).
cy(clk)
EMC_BLSx
EMC_CSx
EMC_WE
EMC_OE
EMC_Ax
EMC_Dx
= 1/CCLK (see LPC178x/7x User manual UM10470).
Dynamic characteristics: Static external memory interface
Parameter
BLS LOW to BLS HIGH time WR
BLS HIGH to end of write
time
BLS HIGH to data invalid
time
amb
=

40
[1]

C to 85
n

or WD
C, V
DD(IO)
RD
DD(REG)(3V3)
n
RD
2
in
1
for rising edges and 60 % of V
Figure 15
RD
Conditions
WR
WR12;
PB = 0
All information provided in this document is subject to legal disclaimers.
5
10
11
; PB = 0
; PB = 0
RD
Rev. 3 — 27 December 2011
= 3.0 V to 3.6 V. Values guaranteed by design.
RD
as indicated in the Conditions column.
5
RD
5
4
[1]
[3]
[6]
[3]
[3]
Min
(WAITWR 
WAITWEN + 1) 
T
<tbd>
<tbd>
cy(clk)
EOR
RD
RD
DD(IO)
6
+ <tbd>
7
for falling edges.
WR
…continued
WR
2
9
32-bit ARM Cortex-M3 microcontroller
Typ
(WAITWR 
WAITWEN + 1) 
T
<tbd>
<tbd>
cy(clk)
WR
WR
1
10
+ <tbd>
WR
12
WR
LPC178x/7x
11
Max
(WAITWR 
WAITWEN + 1) 
T
<tbd>
<tbd>
cy(clk)
EOW
© NXP B.V. 2011. All rights reserved.
+ <tbd>
WR
002aag214
8
82 of 120
Unit
ns
ns
ns