LPC1820FET100 NXP Semiconductors, LPC1820FET100 Datasheet - Page 150

• Manufacturer Part Number: LPC1820FET100
• Description: The LPC1820FET100 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 168 kB of SRAM, and advanced peripherals including High Speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
18. Revision history
Table 35.
LPC1850_30_20_10
Preliminary data sheet
Document ID
LPC1850_30_20_10 v.3.1
LPC1850_30_20_10 v.3
Modifications:
Revision history
Release date Data sheet status
20111215
20111206
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Security engine changed to decryption throughout.
SPIFI boot pins added in
V
V
Figure 29 and Figure 30 updated.
UART and USART maximum bit rates specified in Section 11.7.
Defined 5 V tolerant pins for V
Added pin characteristics for USB1 pins in Table 8.
Added explanation of parameter R
SPIFI driver removed from ROM (Table 4 and Table 5).
Multiple <tbd> replaced in Section 8, Section 9, Section 10, Section 11.
Parameter C
ESD parameter added in Table 6.
AES removed from memory maps.
SD/MMC timing parameters added in Table 23.
LCD timing parameters added in Table 24.
EMC SDRAM timing parameters updated in Table 19.
SSP timing parameters added in Table 16.
USART timing parameters added in Table 15.
DAC characterization data added in Table 26.
DBGEN pin reset state: PD removed (Table 3).
TDO pin reset state: PU removed (Table 3).
USB0_ID pin: pin description updated (Table 3).
USB0_VBUS pin: pin description updated (Table 3).
Static characteristics for LPC1850/30/20/10 Rev ‘-’ moved to Section 16.
Dynamic characteristics added for the crystal oscillator (Section 11.3).
Pin function USB0_PWR_EN changed to USB0_PPWR and description updated in
Table 3.
Pin function USB1_VBUS_EN changed to USB1_PPWR and description updated in
Table 3.
DDA(3V3)
DD(IO)
All information provided in this document is subject to legal disclaimers.
and V
Rev. 3.1 — 15 December 2011
minimum value changed to 2.2 V.
Preliminary data sheet
Preliminary data sheet
ia
DD(REG)(3V3)
= 2 pF updated in Table 25.
Table 4
ranges added to static and dynamic characteristics tables.
DD(IO)
and
vsi
present only in Table 3.
(Figure 36).
Table
Change notice Supersedes
-
-
32-bit ARM Cortex-M3 microcontroller
5.
LPC1850/30/20/10
LPC1850_30_20_10 v.3.0
LPC1850_30_20_10 v.2.2
© NXP B.V. 2011. All rights reserved.
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