LPC2157_2158 NXP Semiconductors, LPC2157_2158 Datasheet
LPC2157_2158
Related parts for LPC2157_2158
LPC2157_2158 Summary of contents
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LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers; 512 kB flash, with 32 segment x 4 LCD driver Rev. 02 — 9 February 2009 1. General description The LPC2157/2158 is a multi-chip module consisting of a LPC2138/2148 single-chip microcontroller combined with a PCF8576D Universal ...
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... NXP Semiconductors 4. Block diagram P0[31:28], P0[27:26] P0[25], P0[23:0] (1) LPC2157 only. Fig 1. LPC2157_2158_2 Product data sheet P1[31:25], P1[17:16] LPC2157/ LPC2158 (1) , MCU Block diagram of LPC2157/2158 Rev. 02 — 9 February 2009 LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers PCF8576D LCD CONTROLLER 002aad382 © NXP B.V. 2009. All rights reserved. S[31:0] BP[3:0] V LCD ...
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... P0[31:28] and GENERAL P0[25:0] PURPOSE I/O P1[31:16] PWM[6:1] (1) Pins shared with GPIO. (2) USB DMA controller with RAM accessible as general purpose RAM and/or DMA is available in LPC2158 only. (3) LPC2157 only. Fig 2. Microcontroller section block diagram LPC2157_2158_2 Product data sheet (1) (1) TMS TDI (1) (1) (1) TRST TCK TDO ...
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... LCD CLK TIMING SYNC OSCILLATOR OSC V SS SCL_LCD INPUT FILTERS SDA_LCD Fig 3. LCD display controller block diagram 5. Pinning information 5.1 Pinning Fig 4. LPC2157_2158_2 Product data sheet BP0 BP1 BP2 BP3 BACKPLANE OUTPUTS LCD VOLTAGE SELECTOR BLINKER DISPLAY CONTROLLER POWER- ON RESET COMMAND DECODER ...
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... MAT0[0]/EINT1 [4] P0[4]/SCK0/ 15 CAP0[1]/AD0[6] [4] P0[5]/MISO0/ 17 MAT0[1]/AD0[7] LPC2157_2158_2 Product data sheet 1 LPC2158FBD 25 Pin configuration for LPC2158 Type Description I/O Port 0: Port 32-bit I/O port with individual direction controls for each bit. Total of 31 pins of the Port 0 can be used as a general purpose bidirectional digital I/Os while P0[31] is output only pin ...
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... P0[12]/DSR1/ 24 MAT1[0]/AD1[3] [4] P0[13]/DTR1/ 25 MAT1[1]/AD1[4] [3] P0[14]/DCD1/ 26 EINT1/SDA1 LPC2157_2158_2 Product data sheet …continued Type Description I/O P0[6] — General purpose input/output digital pin (GPIO). I/O MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data input to SPI slave. I CAP0[2] — Capture input for Timer 0, channel 2. ...
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... P0[22]/AD1[7]/ 92 CAP0[0]/ MAT0[0] [1] P0[23] 84 [5] P0[25]/AD0[4]/ 97 AOUT [7] P0[26]/AD0[5] 98 LPC2157_2158_2 Product data sheet …continued Type Description I/O P0[15] — General purpose input/output digital pin (GPIO). I RI1 — Ring Indicator input for UART1. I EINT2 — External interrupt 2 input. I AD1[5] — ADC 1, input 5. I/O P0[16] — General purpose input/output digital pin (GPIO). ...
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... P1[28]/TDI 86 [6] P1[29]/TCK 82 [6] P1[30]/TMS 78 [6] P1[31]/TRST 8 LPC2157_2158_2 Product data sheet …continued Type Description I/O P0[27] — General purpose input/output digital pin (GPIO). I AD0[0] — ADC 0, input 0. This analog input is always connected to its pin. I CAP0[1] — Capture input for Timer 0, channel 1. O MAT0[1] — Match output for Timer 0, channel 1. ...
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... Pad is designed in accordance with the Universal Serial Bus (USB) specification, revision 2.0 (Full-speed and Low-speed mode only). [ tolerant pad providing digital input (with TTL levels and hysteresis) function only. [9] Pad provides special analog functionality. LPC2157_2158_2 Product data sheet …continued Type Description ...
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... P0[7]/SSEL0/ 19 PWM2/EINT2 [4] P0[8]/TXD1/ 20 PWM4/AD1[1] LPC2157_2158_2 Product data sheet Type Description I/O Port 0: Port 32-bit I/O port with individual direction controls for each bit. Total of 29 pins of the Port 0 can be used as a general purpose bidirectional digital I/Os while P0[31] is output only pin. The operation of port 0 pins depends upon the pin function selected via the pin connect block ...
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... EINT1/SDA1 [4] P0[15]/RI1/ 28 EINT2/AD1[5] [2] P0[16]/EINT0/ 29 MAT0[2]/CAP0[2] [1] P0[17]/CAP1[2]/ 30 SCK1/MAT1[2] LPC2157_2158_2 Product data sheet …continued Type Description I/O P0[9] — General purpose input/output digital pin (GPIO). I RXD1 — Receiver input for UART1. O PWM6 — Pulse Width Modulator output 6. I EINT3 — External interrupt 3 input. I/O P0[10] — General purpose input/output digital pin (GPIO). ...
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... CAP0[2]/MAT0[2] [4] P0[29]/AD0[2]/ 2 CAP0[3]/MAT0[3] [4] P0[30]/AD0[3]/ 3 EINT3/CAP0[0] LPC2157_2158_2 Product data sheet …continued Type Description I/O P0[18] — General purpose input/output digital pin (GPIO). I CAP1[3] — Capture input for Timer 1, channel 3. I/O MISO1 — Master In Slave Out for SSP. Data input to SPI master or data output from SSP slave ...
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... RTCX2 13, 32, SS 39, 40, 85, 95 LPC2157_2158_2 Product data sheet …continued Type Description O P0[31] — General purpose output only digital pin. O UP_LED — USB GoodLink LED indicator LOW when device is configured (non-control endpoints enabled HIGH when the device is not configured or during global suspend ...
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... Pad is designed in accordance with the Universal Serial Bus (USB) specification, revision 2.0 (Full-speed and Low-speed mode only). [ tolerant pad providing digital input (with TTL levels and hysteresis) function only. [9] Pad provides special analog functionality. LPC2157_2158_2 Product data sheet …continued Type Description 3 ...
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... On-chip static RAM On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bit, 16-bit, and 32-bit. The LPC2157/2158 provide 32 kB and static RAM. LPC2157_2158_2 Product data sheet Single-chip 16-bit/32-bit microcontrollers Rev. 02 — 9 February 2009 LPC2157/2158 © ...
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... Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. LPC2157_2158_2 Product data sheet control”. 4.0 GB AHB PERIPHERALS 3 ...
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... LPC2157/2158 introduce accelerated GPIO functions over prior LPC2000 devices: • GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing. LPC2157_2158_2 Product data sheet Single-chip 16-bit/32-bit microcontrollers 2 ...
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... The host controller allocates the USB bandwidth to attached devices through a token based protocol. The bus supports hot plugging, unplugging, and dynamic configuration of the devices. All transactions are initiated by the host controller. LPC2157_2158_2 Product data sheet Single-chip 16-bit/32-bit microcontrollers VREF Rev. 02 — ...
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... Transmission FIFO control enables implementation of software (XON/XOFF) flow control on both UARTs. • LPC2158 UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). LPC2157_2158_2 Product data sheet Single-chip 16-bit/32-bit microcontrollers Rev. 02 — 9 February 2009 LPC2157/2158 © ...
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... SSP serial I/O controller The LPC2157/2158 each contain one Serial Synchronous Port controller (SSP). The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. However, only a single master and a single LPC2157_2158_2 Product data sheet 2 2 C-bus interface ...
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... Four external outputs per timer/counter corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. LPC2157_2158_2 Product data sheet Single-chip 16-bit/32-bit microcontrollers Rev. 02 — 9 February 2009 LPC2157/2158 © NXP B.V. 2009. All rights reserved. ...
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... The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. LPC2157_2158_2 Product data sheet 256 cy(PCLK) 4. Rev. 02 — ...
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... Software must ‘release’ new match values before they can become effective. • May be used as a standard timer if the PWM mode is not enabled. • A 32-bit Timer/Counter with a programmable 32-bit prescaler. LPC2157_2158_2 Product data sheet Single-chip 16-bit/32-bit microcontrollers Rev. 02 — 9 February 2009 LPC2157/2158 © NXP B.V. 2009. All rights reserved. ...
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... V and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. LPC2157_2158_2 Product data sheet Single-chip 16-bit/32-bit microcontrollers and the ARM processor clock frequency is osc Section 6.19.2 “ ...
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... Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses. LPC2157_2158_2 Product data sheet Single-chip 16-bit/32-bit microcontrollers pins falls below 2.6 V. This reset prevents alteration of the DD Rev. 02 — ...
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... The DCC allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The DCC data and control registers are mapped in to addresses in the EmbeddedICE logic. LPC2157_2158_2 Product data sheet Single-chip 16-bit/32-bit microcontrollers ...
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... LCD bias voltages LCD biasing voltages are obtained from an internal voltage divider consisting of three series resistors connected between V compensated externally via the supply to pin V multiplexing of the LCD based on programmable configurations. LPC2157_2158_2 Product data sheet 2 2 C-bus. The I C-bus clock and data signals for both the microcontroller and the ...
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... BP1, BP2 and BP3 respectively. 6.21.10 Data pointer The Display RAM is addressed using the data pointer. Either a single byte or a series of display bytes may be loaded into any location of the display RAM. LPC2157_2158_2 Product data sheet Single-chip 16-bit/32-bit microcontrollers /24. ...
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... The LCD controller acts subaddress inputs A0, A1 and A2 are tied to V 6.21.14 Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. LPC2157_2158_2 Product data sheet Blinking frequencies Normal operating mode ratio Normal blink frequency - ...
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... C-bus slave addresses 2 The I C-bus slave address is 0111 0000. The LCD controller is a write-only device and will not respond to a read access. LPC2157_2158_2 Product data sheet Single-chip 16-bit/32-bit microcontrollers Rev. 02 — 9 February 2009 LPC2157/2158 © NXP B.V. 2009. All rights reserved. ...
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... Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V otherwise noted. [2] Including voltage on outputs in 3-state mode. [3] Not to exceed 4.6 V. [4] The peak current is limited to 25 times the corresponding maximum current. [5] Dependent on package type. LPC2157_2158_2 Product data sheet Single-chip 16-bit/32-bit microcontrollers [1] Conditions for the RTC on ADC related pins [ tolerant I/O pins ...
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... I HIGH-level output OH current I LOW-level output OL current I HIGH-level short-circuit OHS output current I LOW-level short-circuit OLS output current I pull-down current pd I pull-up current pu LPC2157_2158_2 Product data sheet Conditions pull- pull-down pull-up/down (0.5V ) < V < (1. ...
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... LOW-level input voltage IL V hysteresis voltage hys V LOW-level output OL voltage I input leakage current LI Oscillator pins V input voltage on pin i(XTAL1) XTAL1 LPC2157_2158_2 Product data sheet …continued Conditions amb code while(1){} executed from flash, no active peripherals CCLK = 10 MHz CCLK = 60 MHz ...
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... Allowed as long as the current limit does not exceed the maximum current allowed by the device. [10] Minimum condition for V = 4.5 V, maximum condition for V I [11] Applies to P1[16] to P1[31]. [12] On pin VBAT. [13] Optimized for low battery consumption. [14 [15] Includes external resistors of 18 LPC2157_2158_2 Product data sheet …continued Conditions 0 V < V < 3 |(D includes V range ...
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... See [6] The absolute error ( the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC T and the ideal transfer curve. See [7] See Figure 8. LPC2157_2158_2 Product data sheet Conditions 3.3 V SSA DDA ...
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... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 7. ADC characteristics LPC2157_2158_2 Product data sheet (2) (5) (4) (3) 1 LSB (ideal) 1018 ...
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... NXP Semiconductors ADx[y] Fig 8. Suggested ADC interface - LPC2157/2158 ADx[y] pin LPC2157_2158_2 Product data sheet LPC2XXX 20 k SAMPLE Rev. 02 — 9 February 2009 LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers R vsi ADx[y] V EXT 002aad458 © NXP B.V. 2009. All rights reserved ...
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... Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [3] Bus capacitance C in pF, from 400 pF. b LPC2157_2158_2 Product data sheet , unless otherwise specified. DD Conditions ...
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... PERIOD differential data lines Fig 10. Differential data-to-EOP transition skew and EOP width 10. Application information 10.1 Suggested USB interface solutions LPC2158 Fig 11. LPC2158 USB interface using the CONNECT function on pin 17 LPC2157_2158_2 Product data sheet t t CHCL CLCX i(RMS) crossover point crossover point ...
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... NXP Semiconductors LPC2158 Fig 12. LPC2158 USB interface using the UP_LED function on pin 17 LPC2157_2158_2 Product data sheet Single-chip 16-bit/32-bit microcontrollers 1.5 k UP_LED VBUS Rev. 02 — 9 February 2009 LPC2157/2158 USB-B connector 002aad411 © NXP B.V. 2009. All rights reserved. ...
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... UNIT max. 0.15 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT407-1 136E20 Fig 13. Package outline SOT407-1 (LQFP100) LPC2157_2158_2 Product data sheet ...
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... ISP JTAG MCU PLL POR PWM RC SPI SSI SSP TTL UART LPC2157_2158_2 Product data sheet Abbreviations Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Brown-Out Detection Digital-to-Analog Converter Debug Communications Channel Direct Memory Access ...
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... JTAG clock condition (last paragraph) characteristics” 0.4 V moved from Typ to Min column hys characteristics”: added table note [7] Product data sheet Rev. 02 — 9 February 2009 LPC2157/2158 Change notice Supersedes - LPC2157_2158_1 - - © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 15. Contact information For more information, please visit: For sales office addresses, please send an email to: LPC2157_2158_2 Product data sheet [3] Definition This document contains data from the objective specification for product development. ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: LPC2157_2158_2 All rights reserved. Date of release: 9 February 2009 ...