LPC2926_27_29 NXP Semiconductors, LPC2926_27_29 Datasheet

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LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB Rev. 5 — 28 September 2010 1. General description The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCM blocks operating at frequencies 125 MHz, Full-speed USB 2.0 ...

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... CPU operating voltage: 1.8 V ± I/O operating voltage: 2 3.6 V; inputs tolerant up to 5.5 V. 144-pin LQFP package. −40 °C to +85 °C ambient operating temperature range. LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 © ...

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... Note that parts LPC2926, LPC2927 and LPC2929 are not fully pin compatible with parts LPC2917, LPC2919 and LPC2917/01, LPC2919/01. The Modulation and Sampling Control SubSystem (MSCSS) and timer blocks have a reduced pinout on the LPC2926/2927/2929. LPC2926_27_29 Product data sheet Description SRAM SMC ...

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... V ADC1 ADC0 QUADRATURE ENCODER CAN0/1 GLOBAL ACCEPTANCE FILTER UART/LIN0/1 I2C0/1 Grey-shaded blocks represent peripherals and memory regions accessible by the GPDMA. Fig 1. LPC2926/2927/2929 block diagram LPC2926_27_29 Product data sheet JTAG interface TEST/DEBUG INTERFACE ITCM DTCM 8 kB SRAM ARM968E-S 1 master ...

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... RXDC1/SDO2 [1] P0[26]/TXD1/SDI2 5 [1] P0[27]/RXD1/SCK2 6 [1] P0[28]/CAP0[0]/ 7 MAT0[0] [1] P0[29]/CAP0[1]/ 8 MAT0[ DD(IO) LPC2926_27_29 Product data sheet 1 LPC2926FBD144 LPC2927FBD144 LPC2929FBD144 36 Pin configuration for SOT486-1 (LQFP144) Description Function 0 Function 1 (default) IEEE 1149.1 test data out GPIO2, pin 21 SPI2 SDI GPIO0, pin 24 UART1 TXD GPIO0, pin 25 ...

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... TRAP3/PMAT3[ DD(IO) [1] P1[25]/PMAT1[0]/ 32 USB_VBUS/ PMAT3[1] [1] P1[24]/PMAT0[0]/ 33 USB_CONNECT/ PMAT3[0] [1] P1[23]/RXD0/ 34 USB_SSPND/CS5 LPC2926_27_29 Product data sheet …continued Description Function 0 Function 1 (default) GPIO2, pin 22 SPI2 SCK GPIO2, pin 23 SPI1 SCS0 GPIO3, pin 6 SPI0 SCS3 GPIO3, pin 7 SPI2 SCS1 GPIO0, pin 30 - GPIO0, pin 31 - GPIO2, pin 24 ...

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... P2[3]/MAT2[3]/ 55 TRAP0/D11 [1] P1[11]/SCK1/ 56 SCL0/CS3 [1] P1[10]/SDI1/ 57 SDA0/CS2 [1] P3[12]/SCS1[0]/EI4/ 58 USB_SSPND LPC2926_27_29 Product data sheet …continued Description Function 0 Function 1 (default) GPIO1, pin 22 UART0 TXD IEEE 1149.1 test mode select, pulled up internally IEEE 1149.1 test clock GPIO1, pin 21 TIMER3 CAP3 GPIO1, pin 20 TIMER3 CAP2 ...

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... EI7/RXDC0 V 82 DD(IO) [1] P2[8]/CLK_OUT/ 83 PMAT0[0]/SCS0[2] [1] P2[9]/ 84 USB_UP_LED/ PMAT0[1]/ SCS0[1] LPC2926_27_29 Product data sheet …continued Description Function 0 Function 1 (default) ground for digital core 1.8 V power supply for digital core GPIO3, pin 13 SPI1 SDO GPIO2, pin 4 TIMER1 MAT0 GPIO2, pin 5 TIMER1 MAT1 GPIO1, pin 9 ...

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... P0[6]/IN0[2]/ 105 PMAT0[4]/D30 [1] P0[7]/IN0[3]/ 106 PMAT0[5]/D31 V 107 DDA(ADC3V3) [1] JTAGSEL 108 LPC2926_27_29 Product data sheet …continued Description Function 0 Function 1 (default) GPIO1, pin 3 SPI2 SCS1 GPIO1, pin 2 SPI2 SCS3 GPIO1, pin 1 EXTINT1 ground for digital core 1.8 V power supply for digital core ...

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... PCAP0[2]/BLS2 [1] P2[17]/RXD1/ 130 PCAP1[0]/BLS3 V 131 DD(IO) [4] P0[18]/IN2[2]/ 132 PMAT2[0]/A14 LPC2926_27_29 Product data sheet …continued Description Function 0 Function 1 (default supply voltage for ADC0 and 5 V reference for ADC0. HIGH reference for ADC LOW reference for ADC GPIO0, pin 8 ADC1 IN0 ...

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... Power, Clock and Reset Control cluster (also called subsystem). • Three ARM Peripheral Buses (APB - a compatible superset of ARM's AMBA advanced peripheral bus) for connection to on-chip peripherals clustered in subsystems. • One ARM Peripheral Bus for event router and system control. LPC2926_27_29 Product data sheet …continued Description Function 0 Function 1 (default) ...

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... THUMB code can provide the code size of ARM, and 160 % of the performance of an equivalent ARM controller connected to a 16-bit memory system. The ARM968E-S processor is described in detail in the ARM968E-S data sheet LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB All information provided in this document is subject to legal disclaimers. Rev. 5 — ...

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... In addition SRAM for the ETB can be used as static memory for code and data storage. However, DMA access to this memory region is not supported. LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB All information provided in this document is subject to legal disclaimers. ...

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Memory map LPC2926/2927/2929 0xFFFF FFFF VIC 0xFFFF F000 PCR/VIC reserved 0xFFFF C000 subsystem CGU1 0xFFFF B000 PMU 0xFFFF A000 RGU 0xFFFF 9000 CGU0 0xFFFF 8000 0xE00E 0000 reserved 0xE00C A000 quadrature encoder 0xE00C 9000 PWM3 0xE00C 8000 PWM2 0xE00C ...

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... JTAGSEL TRST TMS TDI TDO TCK 1. Only for 1.8 V power sources LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Section 8 for trip levels of the internal power-up reset circuit for characteristics of the several start-up and initialization times. Reset pin Direction ...

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... Management Unit (PMU) and can be controlled independently. Branch clocks derived from the same base clock are synchronous in frequency and phase. See more details of clock and power control within the device. LPC2926_27_29 Product data sheet shows the power supply pins. Power supply pins Description digital core supply 1 ...

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... SYSTEM CONTROL EVENT ROUTER CFID peripheral subsystem GPIO0/1/2/3/5 TIMER 0/1/2/3 SPI0/1/2 UART0/1 WDT Fig 4. LPC2926/2927/2929 overview of clock areas LPC2926_27_29 Product data sheet BA SE_ICLK0_CLK BASE_SYS_CLK BASE_ICLK1_CLK BASE_IVNSS_CLK branch clocks BASE_PCR_CLK BASE_MSCSS_CLK CGU0 All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 ...

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... Table 7. Base clock BASE_SAFE_CLK BASE_SYS_CLK BASE_PCR_CLK BASE_IVNSS_CLK LPC2926_27_29 Product data sheet contains an overview of all the base blocks in the LPC2926/2927/2929 and their for more details of how to control the individual branch clocks. CGU0 base clock and branch clock overview Branch clock name CLK_SAFE ...

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... In the Power Clock and Reset Control subsystem parts of the CGU, RGU, and PMU have their own clock source. See Table 8. Base clock BASE_OUT_CLK BASE_USB_CLK BASE_USB_I2C_CLK LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB CGU0 base clock and branch clock overview Branch clock name CLK_MSCSS_APB CLK_MSCSS_MTMR0 ...

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... When an AHB data-port read transfer requires data from the same flash word as the previous read transfer, no new flash read is done and the read data is given without wait cycles. LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB All information provided in this document is subject to legal disclaimers. Rev. 5 — ...

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... The flash memory also has sector-wise protection. Writing occurs per page which consists of 4096 bits (32 flash words). A small sector contains 16 pages; a large sector contains 128 pages. LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB ...

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... These depend on flash memory response time and system clock period. The minimum wait-states value can be calculated with the following formulas: Synchronous reading: > WST Asynchronous reading: > WST LPC2926_27_29 Product data sheet gives an overview of the flash-sector base addresses. Flash sector overview Sector size (kB ...

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... A separate chip select output is available for each bank. The chip select lines are configurable to be active HIGH or LOW. Memory-bank selection is controlled by memory addressing. memory base addresses, chip selects, and bank internal addresses. LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Table 11 shows how the 32-bit system address is mapped to the external bus All information provided in this document is subject to legal disclaimers ...

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... The External Static Memory Controller is clocked by CLK_SYS_SMC, see 6.9.4 External memory timing diagrams A timing diagram for reading from external memory is shown in between the wait-state settings is indicated with arrows. LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB External memory-bank address bit description ...

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... NXP Semiconductors Fig 5. A timing diagram for writing to external memory is shown In between wait-state settings is indicated with arrows. (1) BLS has the same timing configurations that use the byte lane enable signals to connect Fig 6. LPC2926_27_29 Product data sheet CLK(SYS WSTOEN ...

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... DMA support for peripherals The GPDMA supports the following peripherals: SPI0/1/2 and UART0/1. The GPDMA can access both embedded SRAM blocks (16 kB and 32 kB), both TCMs, external static memory, and flash memory. LPC2926_27_29 Product data sheet ...

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... USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the device controller, and a master-only I implement OTG dual-role device functionality. The dedicated I external OTG transceiver. LPC2926_27_29 Product data sheet 6.7.2. 10.2. All information provided in this document is subject to legal disclaimers. ...

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... USB_SSPND O 6.11.4 Clock description Access to the USB registers is clocked by the CLK_SYS_USB, derived from BASE_SYS_CLK, see the USB block, BASE_USB_CLK and BASE_USB_I2C_CLK (see LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Description V status input. When this function is not enabled BUS via its corresponding PINSEL register driven HIGH internally ...

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... The event router allows the event source to be defined, its polarity and activation type to be selected and the interrupt to be masked or enabled. The event router can be used to start a clock on an external event. The vectored interrupt-controller inputs are active HIGH. LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB 2 C-bus SCL pins plus three internal event All information provided in this document is subject to legal disclaimers ...

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... Key features: • Internal chip reset if not periodically triggered • Timer counter register runs on always-on safe clock • Optional interrupt generation on watchdog time-out LPC2926_27_29 Product data sheet shows the pins connected to the event router. Event-router pin connections Direction Description I external interrupt input ...

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... Four 32-bit match registers per timer that allow: – Continuous operation with optional interrupt generation on match – Stop timer on match with optional interrupt generation – Reset timer on match with optional interrupt generation LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Section 6 ...

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... The frequency of all these clocks is identical as they are derived from the same base clock BASE_CLK_TMR. The register interface towards the system bus is clocked by CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_TMRx. LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Section 6.16.5 ...

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... Supports timer-triggered operation. • Programmable clock bit rate and prescale based on SPI source clock (BASE_SPI_CLK), independent of system clock. • Separate transmit and receive FIFO memory buffers; 16 bits wide, 32 locations deep. LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Section 6.14.2). Table 17 shows the UART pins (x runs from ...

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... MSB. 6.13.5.2 Pin description The SPI pins are combined with other functions on the port pins of the LPC2926/2927/2929, see y runs from 0 to 3). Table 18. Symbol SPIx SCSy LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Section 6.12.3. SPI pins Pin name Direction ...

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... The five GPIO ports in the LPC2926/2927/2929 have the pins listed below. The GPIO pins are combined with other functions on the port pins of the LPC2926/2927/2929. shows the GPIO pins. LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB SPI pins … ...

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... It can contain up to 1024 standard frame identifiers or 512 extended frame identifiers or a mixture of both types also possible to define identifier groups for standard and extended message formats. LPC2926_27_29 Product data sheet GPIO pins ...

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... Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver transmitter with the capability to both receive and send information (such as memory). Transmitters and/or LPC2926_27_29 Product data sheet shows the CAN pins (x runs from 0 to 1). ...

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... Two dedicated timers to schedule and synchronize the PWMs and ADCs • Quadrature encoder interface 6.15.1 Functional description The MSCSS contains Pulse Width Modulators (PWMs), Analog-to-Digital Converters (ADCs) and timers. LPC2926_27_29 Product data sheet 2 C-bus interfaces are: 2 C-bus can be used for test and diagnostic purposes. ...

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... To support applications like motor control, a mechanism to synchronize several PWMs and ADCs is available (sync_in and sync_out). Note that the PWMs run on the PWM clock and the ADCs on the ADC clock, see Section LPC2926_27_29 Product data sheet provides an overview of the MSCSS. An AHB-to-APB bus bridge takes care of 6.16.2. ...

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... NXP Semiconductors MSCSS PAUSE Fig 8. Modulation and Sampling Control SubSystem (MSCSS) block diagram LPC2926_27_29 Product data sheet AHB-TO-APB BRIDGE QEI ADC0 start synch start ADC1 MSCSS TIMER0 start synch start ADC2 PWM0 carrier synch carrier PWM1 carrier MSCSS TIMER1 carrier ...

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... Optional compare condition to generate a ‘less than’ ‘equal to or greater than’ compare-value indication for each channel. • Power-down mode. LPC2926_27_29 Product data sheet Section 6.15.4.2. Pins connected to the four PWM modules are described in 6.15.5.4, pins directly connected to the MSCSS timer 1 module are described in 6 ...

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... The three ADC modules in the MSCSS have the pins described below. The ADCx input pins are combined with other functions on the port pins of the LPC2926/2927/2929. The VREFN and VREFP pins are common to all ADCs. LPC2926_27_29 Product data sheet Figure 9, shows the basic architecture of each ADC. The ADC Section 6 ...

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... BASE_ADC_CLK. The register interface towards the system bus is clocked by CLK_MSCSS_ADCx_APB. Control logic for the analog section of the ADC is clocked by CLK_ADCx, see also Figure 9. LPC2926_27_29 Product data sheet ADC pins Pin name Direction Description ...

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... Motor controller: The PWM provides multi-phase outputs, and these outputs can be controlled to have a certain pattern sequence. In this way the force/torque of the motor can be adjusted as desired. This makes the PWM function as a motor drive. LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB All information provided in this document is subject to legal disclaimers. Rev. 5 — ...

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... Several PWMs can be synchronized using the trans_enable_in/trans_enable_out and sync_in/sync_out ports. See Figure 8 LPC2926/2927/2929. PWM 0 can be master over PWM 1; PWM 1 can be master over PWM 2, etc. LPC2926_27_29 Product data sheet APB DOMAIN update capture data PWM ...

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... These signals are instead connected to the ADC and PWM modules as outlined in the description of the MSCSS, see See Section 6.13.3 LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB PWM pins Pin name ...

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... Digital filter with programmable delays for encoder input signals. • Can accept decoded signal inputs (clk and direction). • Connected to APB. LPC2926_27_29 Product data sheet MSCSS timer 1 pin Direction Description IN pause pin for MSCSS timer 1 6.7.2. Note that each timer has its own CLK_MSCSS_MTMRx branch clock for All information provided in this document is subject to legal disclaimers. Rev. 5 — ...

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... The Power, Clock and Reset Control Subsystem in the LPC2926/2927/2929 includes the Clock Generator Units (CGU0 and CGU1), a Reset Generator Unit (RGU) and a Power Management Unit (PMU). Figure 11 communication with the AHB system bus. LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB QEI pins Pin name ...

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... AHB side of the AHB to DTL bus bridge and CLK_PCR_SLOW clocks the CGU, RGU and PMU internal logic, see BASE_SYS_CLK, which can be switched off in low-power modes. CLK_PCR_SLOW is derived from BASE_PCR_CLK and is always on in order to be able to wake up from low-power modes. LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB CGU0 PLL ...

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... Maximum frequency that guarantees stable operation of the LPC2926/2927/2929. [2] Fixed to low-power oscillator. For generation of these base clocks, the CGU consists of primary and secondary clock generators and one output generator for each base clock. LPC2926_27_29 Product data sheet CGU0 base clocks Frequency (MHz) BASE_SAFE_CLK 0 ...

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... The crystal oscillator can be used as source for high-frequency clocks external clock input if a crystal is not connected. Secondary clock generators are a PLL and seven fractional dividers (FDIV[0:6]). The PLL has three clock outputs: normal, 120° phase-shifted and 240° phase-shifted. LPC2926_27_29 Product data sheet FDIV0 clkout ...

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... Clock Activity Detection: and values of ‘CLK_SEL’ that would select those clocks are masked and not written to the control registers. This is accomplished by adding a clock detector to every clock LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB For every output generator generating the base clocks a ...

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... PLL has locked onto the input clock. 2. Generation of the main clock is restricted by the frequency range of the PLL clock input. See LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Provisions are included in the CGU to allow clocks to be Figure . These clocks are either divided by 2 × ...

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... LOCK signal high once it has regained lock on the input clock. 6.16.2.3 Pin description The CGU0 module in the LPC2926/2927/2929 has the pins listed in Table 28. Symbol XOUT_OSC XIN_OSC LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB PSEL bits / 2PDIV bypass / MDIV MSEL bits ...

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... Reset Generation Unit (RGU) The RGU controls all internal resets. The key features of the Reset Generation Unit (RGU) are: • Reset controlled individually per subsystem LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB (CGU1) FDIV0 AHB TO DTL BRIDGE ...

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... MSCSS_A2V_RST MSCSS_PWM_RST MSCSS_ADC_RST MSCSS_TMR_RST I2C_RST QEI_RST DMA_RST USB_RST VIC_RST AHB_RST LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Reset output configuration Reset source power-on reset module POR_RST, RST pin RGU_RST, WATCHDOG PCR internal; is source for COLD_RST PCR_RST COLD_RST ...

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... Remark: For any disabled branch clocks to be re-activated their corresponding base clocks must be running (controlled by CGU0). Table 32 Every branch clock is related to one particular base clock not possible to switch the source of a branch clock in the PMU. LPC2926_27_29 Product data sheet RGU pins Direction Description IN external reset input, Active LOW ...

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... CLK_IVNSS_CANC1 CLK_IVNSS_I2C0 CLK_IVNSS_I2C1 CLK_IVNSS_LIN0 CLK_IVNSS_LIN1 CLK_MSCSS_APB CLK_MSCSS_MTMR0 CLK_MSCSS_MTMR1 CLK_MSCSS_PWM0 CLK_MSCSS_PWM1 CLK_MSCSS_PWM2 CLK_MSCSS_PWM3 CLK_MSCSS_ADC0_APB BASE_MSCSS_CLK CLK_MSCSS_ADC1_APB BASE_MSCSS_CLK LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Branch clock overview Base clock BASE_SAFE_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK ...

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... Software-programmable routing of interrupt requests towards the ARM-processor inputs IRQ and FIQ. • Fast identification of interrupt requests through vector. • Support for nesting of interrupt service routines. LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Branch clock overview …continued Base clock ...

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... Software emulation of an interrupt-requesting device, including interrupts. 6.17.2 Clock description The VIC is clocked by CLK_SYS_VIC, see LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Section All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 6 ...

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... LOW-level short-circuit OLS output current General T storage temperature stg T ambient temperature amb LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Conditions average value per supply pin average value per ground pin for ADC1/2: I/O port 0 pin 8 to pin 23. ...

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... ADC0 is V DDA(ADC5V0) [7] Not exceeding 6 V. [8] 112 mA per should not be exceeded. DD(IO) SS(IO) [9] Human-body model: discharging a 100 pF capacitor via a 10 kΩ series resistor. LPC2926_27_29 Product data sheet Conditions on all pins human body model charged device model on corner pins charged device model . I(ADC) ⁄ performed on the input voltage before feeding into the ADC0 itself ...

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... I 5.0 V ADC analog supply DDA(ADC5V0) current. Input pins and I/O pins configured as input V input voltage I V HIGH-level input voltage IH LPC2926_27_29 Product data sheet = DDA(ADC3V3) Conditions Device state after reset; system clock °C; 125 MHz; T amb executing code while(1){} from flash ...

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... V HIGH-level output voltage (driven) for OH V LOW-level output voltage (driven) for OL I HIGH-level output current LPC2926_27_29 Product data sheet …continued = DDA(ADC3V3) Conditions all port pins, RST, TRST, TDI, JTAGSEL, TMS, TCK all port pins 3.3 V ...

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... This parameter is not part of production testing or final testing, hence only a typical value is stated. Maximum and minimum values are based on simulation results. [10] The power-up reset has a time filter: V for 11 μs before internal reset is asserted. V trip(low) LPC2926_27_29 Product data sheet …continued = DDA(ADC3V3) ...

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... T ADC and the ideal transfer curve. See [8] See Figure 16. ADC IN[y] Fig 16. Suggested ADC interface - LPC2926/2927/2929 ADC1/2 IN[y] pin LPC2926_27_29 Product data sheet − ° ° +85 C unless otherwise specified; ADC frequency 4.5 MHz. ...

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... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 17. ADC characteristics LPC2926_27_29 Product data sheet (2) (5) (4) (3) 1 LSB (ideal (LSB ...

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... NXP Semiconductors 8.1 Power consumption I DD(CORE) (mA) Fig 18 DD(CORE) (mA) Fig 19. I LPC2926_27_29 Product data sheet °C; active mode entered executing code from flash; core voltage 1.8 V; all Conditions: T amb peripherals enabled but not configured to run. at different core frequencies (active mode) ...

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... NXP Semiconductors I DD(CORE) (mA) Fig 20. 8.2 Electrical pin characteristics V (mV) Fig 21. Typical LOW-level output voltage versus LOW-level output current LPC2926_27_29 Product data sheet 80 125 MHz 60 100 MHz 80 MHz 40 40 MHz 20 10 MHz 0 −40 −15 10 Conditions: active mode entered executing code from flash; core voltage 1.8 V; all peripherals enabled but not configured to run ...

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... NXP Semiconductors V Fig 22. Typical HIGH-level output voltage versus HIGH-level output current I (μA) Fig 23. Typical pull-down current versus temperature LPC2926_27_29 Product data sheet 3.5 OH (V) 3.0 2.5 2.0 1.0 2 3.3 V. DD(IO) 80 I(pd −40 − 3 All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 ...

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... NXP Semiconductors I (μA) Fig 24. Typical pull-up current versus temperature LPC2926_27_29 Product data sheet −20 I(pu) −40 −60 −80 −100 −40 − All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB ...

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... This parameter is not part of production testing or final testing, hence only a typical value is stated. [4] Oscillator start-up time depends on the quality of the crystal. For most crystals it takes about 1000 clock pulses until the clock is fully stable. LPC2926_27_29 Product data sheet = 3.6 V; all voltages are measured with respect to ...

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... NXP Semiconductors f ref(RO) (kHz) Fig 25. Low-power ring oscillator thermal characteristics LPC2926_27_29 Product data sheet 520 510 500 490 480 −40 −15 10 All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB 1 ...

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... EOPR1 t EOP width at receiver EOPR2 [1] Characterized but not implemented as production test. Guaranteed by design. T PERIOD differential data lines Fig 26. Differential data-to-EOP transition skew and EOP width LPC2926_27_29 Product data sheet , unless otherwise specified. DD(3V3) Conditions see ...

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... Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. [2] [3] Bus capacitance C in pF, from 400 pF. b LPC2926_27_29 Product data sheet 2 C-bus interface 2 C-bus pins = 3.6 V ...

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... Cased products are tested at T test conditions to cover the specified temperature and power supply voltage range. shifting edges SCKn SDOn SDIn Fig 27. SPI data input set-up time in SSP Master mode LPC2926_27_29 Product data sheet = DDA(ADC3V3) Conditions master operation slave operation = 25 ° ...

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... Number of program/erase cycles. Table 41. − amb V DDA(ADC3V3) Symbol f clk N endu t ret LPC2926_27_29 Product data sheet Flash characteristics ° ° + DD(CORE) DD(OSC_PLL 3.6 V; all voltages are measured with respect to ground. Parameter Conditions endurance retention time powered unpowered programming time ...

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... When the byte lane select signals are used to connect the write enable input (8 bit devices), t [3] When the byte lane select signals are used to connect the write enable input (8 bit devices), t [4] For 16 and 32 bit devices. LPC2926_27_29 Product data sheet = 3.6 V; all voltages are measured with respect to DDA(ADC3V3) ...

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... NXP Semiconductors CSLOEL OE/BLS Fig 28. External memory read access CS BLS Fig 29. External memory write access LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB t CSLAV t su(DQ OELAV BLSLAV OELOEH BLSLBLSH t CSLDV t BLSLBLSH t CSLBLSL t CSLWEL t WELDV ...

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... The LPC2926/2927/2929 is specified to operate at a maximum frequency of 125 MHz, maximum temperature of 85 °C, and maximum core voltage of 1.89 V. Figure 31 LPC2926/2927/2929 by controlling the temperature and the core voltage accordingly. LPC2926_27_29 Product data sheet = 3.6 V; all voltages are measured with respect to ...

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... NXP Semiconductors core frequency (MHz) Fig 30. Core operating frequency versus temperature for different core voltages. core frequency (MHz) Fig 31. Core operating frequency versus core voltage for different temperatures LPC2926_27_29 Product data sheet 145 V = 1.95 V DD(CORE) 135 V = 1.8 V DD(CORE) 125 V = 1.65 V DD(CORE) ...

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... NXP Semiconductors 10.2 Suggested USB interface solutions LPC29xx Fig 32. LPC2926/2927/2929 USB interface on a self-powered device LPC29xx Fig 33. LPC2926/2927/2929 USB interface on a bus-powered device LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO) USB_UP_LED USB_CONNECT SoftConnect switch R1 1.5 kΩ USB_VBUS Ω ...

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... USB_SCL USB_SDA USB_INT USB_D+ USB_D− Fig 34. LPC2926/2927/2929 USB OTG port configuration USB_UP_LED USB_CONNECT LPC29xx USB_D+ USB_D− USB_VBUS Fig 35. LPC2926/2927/2929 USB device port configuration LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO RESET_N ADR/PSW OE_N/INT_N V ...

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... SCKn (CPOL = 1) CPHA = 1 CPHA = 0 Fig 36. SPI timing in master mode SCKn (CPOL = 0) SCKn (CPOL = 1) CPHA = 1 CPHA = 0 Fig 37. SPI timing in slave mode LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB SDOn MSB OUT SDIn MSB IN SDOn MSB OUT DATA VALID ...

Page 85

... PCB as small as possible. Also parasitics should stay as small as possible. Values of C smaller accordingly to the increase in parasitics of the PCB layout. LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB which attenuates the input voltage by a factor C ...

Page 86

... max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT486-1 136E23 Fig 39. Package outline SOT486-1 (LQFP144) LPC2926_27_29 Product data sheet ...

Page 87

... Solder bath specifications, including temperature and impurities LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB All information provided in this document is subject to legal disclaimers. ...

Page 88

... Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB and 45 SnPb eutectic process (from J-STD-020C) Package reflow temperature (° ...

Page 89

... NXP Semiconductors Fig 40. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. LPC2926_27_29 Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers ...

Page 90

... CAN — ISO 11898-1: 2002 road vehicles - Controller Area Network (CAN) - part 1: data link layer and physical signalling [5] LIN — LIN specification package, revision 2.0 LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Abbreviations list Description Advanced High-performance Bus ...

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... NXP Semiconductors 15. Revision history Table 47. Revision history Document ID Release date LPC2926_27_29 v.5 20100928 Modifications: LPC2927_29 v.4 20100414 Modifications: LPC2927_29 v.3 20091208 LPC2927_29 v.2 20090622 LPC2927_29 v.1 20090115 LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Data sheet status Product data sheet • Added LPC2926 device. ...

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... Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB [3] Definition This document contains data from the objective specification for product development ...

Page 93

... NXP Semiconductors’ specifications such use shall be solely at customer’s 17. Contact information For more information, please visit: For sales office addresses, please send an email to: LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

Page 94

... USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.11.1 USB device controller . . . . . . . . . . . . . . . . . . . 27 6.11.2 USB OTG controller . . . . . . . . . . . . . . . . . . . . 27 6.11.3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 28 6.11.4 Clock description . . . . . . . . . . . . . . . . . . . . . . 28 6.12 General subsystem LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB 6.12.1 General subsystem clock description . . . . . . 29 6.12.2 Chip and feature identification . . . . . . . . . . . . 29 6.12.3 System Control Unit (SCU 6.12.4 Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.12.4.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 30 6 ...

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... For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC2926/2927/2929 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 88 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 90 References Revision history . . . . . . . . . . . . . . . . . . . . . . . 91 Legal information . . . . . . . . . . . . . . . . . . . . . . 92 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 92 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Contact information . . . . . . . . . . . . . . . . . . . . 93 Contents Date of release: 28 September 2010 Document identifier: LPC2926_27_29 All rights reserved. ...