P89LPC9331_9341_9351_9361 NXP Semiconductors, P89LPC9331_9341_9351_9361 Datasheet - Page 43
P89LPC9331_9341_9351_9361
Manufacturer Part Number
P89LPC9331_9341_9351_9361
Description
The P89LPC9331/9341/9351/9361 is a single-chip microcontroller, available in low costpackages, based on a high performance processor architecture that executes instructionsin two to four clocks, six times the rate of standard 80C51 devices
Manufacturer
NXP Semiconductors
Datasheet
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P89LPC9331_9341_9351_9361
Product data sheet
7.22.7 Alternating output mode
7.22.8 PLL operation
In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating
pairs for bridge drive control. In this mode the output of these PWM channels are
alternately gated on every counter cycle.
The PWM module features a Phase Locked Loop that can be used to generate a
CCUCLK frequency between 16 MHz and 32 MHz. At this frequency the PWM module
provides ultrasonic PWM frequency with 10-bit resolution provided that the crystal
frequency is 1 MHz or higher. The PLL is fed an input signal from 0.5 MHz to 1 MHz and
generates an output signal of 32 times the input frequency. This signal is used to clock the
timer. The user will have to set a divider that scales PCLK by a factor from 1 to 16. This
divider is found in the SFR register TCR21. The PLL frequency can be expressed as
shown in
Where: N is the value of PLLDV3:0.
PLL frequency
Fig 10. Symmetrical PWM
Fig 11. Alternate output mode
Equation
compare value
=
All information provided in this document is subject to legal disclaimers.
non-inverted
timer value
----------------- -
(
PCLK
N
inverted
1:
TOR2
+
1
Rev. 5 — 10 January 2011
0
)
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC9331/9341/9351/9361
002aaa895
TOR2
COMPARE VALUE A (or C)
COMPARE VALUE B (or D)
0
PWM OUTPUT (OCA or OCC)
PWM OUTPUT (OCB or OCD)
TIMER VALUE
002aaa894
© NXP B.V. 2011. All rights reserved.
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