STM32F103RC

Manufacturer Part NumberSTM32F103RC
DescriptionMainstream Performance line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
ManufacturerSTMicroelectronics
STM32F103RC datasheet
 


Specifications of STM32F103RC

CoreARM 32-bit Cortex™-M3 CPUConversion Range0 to 3.6 V
Dma12-channel DMA controllerSupported Peripheralstimers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
Systick Timera 24-bit downcounter  
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
Page 1/130

Download datasheet (2Mb)Embed
Next
High-density performance line ARM-based 32-bit MCU with 256 to
512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
Features
Core: ARM 32-bit Cortex™-M3 CPU
– 72 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access
– Single-cycle multiplication and hardware
division
Memories
– 256 to 512 Kbytes of Flash memory
– up to 64 Kbytes of SRAM
– Flexible static memory controller with 4
Chip Select. Supports Compact Flash,
SRAM, PSRAM, NOR and NAND memories
– LCD parallel interface, 8080/6800 modes
Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
detector (PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC with calibration
– 32 kHz oscillator for RTC with calibration
Low power
– Sleep, Stop and Standby modes
– V
supply for RTC and backup registers
BAT
3 × 12-bit, 1 µs A/D converters (up to 21
channels)
– Conversion range: 0 to 3.6 V
– Triple-sample and hold capability
– Temperature sensor
2 × 12-bit D/A converters
DMA: 12-channel DMA controller
– Supported peripherals: timers, ADCs, DAC,
2
2
SDIO, I
Ss, SPIs, I
Cs and USARTs
Debug mode
– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M3 Embedded Trace Macrocell™
April 2011
STM32F103xC STM32F103xD
LQFP64 10 × 10 mm,
LQFP100 14 × 14 mm,
LQFP144 20 × 20 mm
Up to 112 fast I/O ports
– 51/80/112 I/Os, all mappable on 16
external interrupt vectors and almost all
5 V-tolerant
Up to 11 timers
– Up to four 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
– 2 × 16-bit motor control PWM timers with
dead-time generation and emergency stop
– 2 × watchdog timers (Independent and
Window)
– SysTick timer: a 24-bit downcounter
– 2 × 16-bit basic timers to drive the DAC
Up to 13 communication interfaces
2
– Up to 2 × I
C interfaces (SMBus/PMBus)
– Up to 5 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 3 SPIs (18 Mbit/s), 2 with I
interface multiplexed
– CAN interface (2.0B Active)
– USB 2.0 full speed interface
– SDIO interface
CRC calculation unit, 96-bit unique ID
®
ECOPACK
packages
Table 1.
Device summary
Reference
STM32F103RC STM32F103VC
STM32F103xC
STM32F103ZC
STM32F103RD STM32F103VD
STM32F103xD
STM32F103ZD
STM32F103RE STM32F103ZE
STM32F103xE
STM32F103VE
Doc ID 14611 Rev 8
STM32F103xE
FBGA
WLCSP64
LFBGA100 10 × 10 mm
LFBGA144 10 × 10 mm
2
S
Part number
1/130
www.st.com
1

STM32F103RC Summary of contents

  • Page 1

    ... CAN interface (2.0B Active) – USB 2.0 full speed interface – SDIO interface ■ CRC calculation unit, 96-bit unique ID ® ■ ECOPACK packages Table 1. Device summary Reference STM32F103RC STM32F103VC STM32F103xC STM32F103ZC STM32F103RD STM32F103VD STM32F103xD STM32F103ZD STM32F103RE STM32F103ZE STM32F103xE STM32F103VE Doc ID 14611 Rev 8 STM32F103xE FBGA WLCSP64 LFBGA100 10 × ...

  • Page 2

    Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 3

    STM32F103xC, STM32F103xD, STM32F103xE 2.3.29 2.3.30 3 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 4

    Contents 5.3.20 5.3.21 6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 5

    STM32F103xC, STM32F103xD, STM32F103xE List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 6

    List of tables Table 45. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 7

    STM32F103xC, STM32F103xD, STM32F103xE List of figures Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram . . . 12 Figure 2. Clock tree . . . . . . . . . . . . . . . . ...

  • Page 8

    List of figures Figure 39. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 9

    ... Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103xC, STM32F103xD and STM32F103xE high-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2.2: Full compatibility throughout the The high-density STM32F103xx datasheet should be read in conjunction with the STM32F10xxx reference manual ...

  • Page 10

    Description 2 Description The STM32F103xC, STM32F103xD and STM32F103xE performance line family incorporates the high-performance ARM 72 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM Kbytes), and an extensive range of enhanced I/Os ...

  • Page 11

    STM32F103xC, STM32F103xD, STM32F103xE 2.1 Device overview The STM32F103xx high-density performance line family offers devices in six different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives ...

  • Page 12

    Description Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram TRACECLK TRACED[0:3] TPIU as AS Trace/trig SW/JTAG NJTRST JTDI JTCK/SWCLK Cortex-M3 CPU JTMS/SWDIO JTDO max : 48/72 MHz NVIC GP DMA1 A[25:0] 7 channels D[15:0] CLK ...

  • Page 13

    STM32F103xC, STM32F103xD, STM32F103xE Figure 2. Clock tree 8 MHz HSI RC PLLSRC OSC_OUT 4-16 MHz HSE OSC OSC_IN OSC32_IN LSE OSC 32.768 kHz OSC32_OUT LSI RC 40 kHz Main Clock Output MCO 1. When the HSI is used as a ...

  • Page 14

    Description 2.2 Full compatibility throughout the family The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are ...

  • Page 15

    STM32F103xC, STM32F103xD, STM32F103xE 2.3 Overview ® 2.3.1 ARM Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets ...

  • Page 16

    Description 2.3.6 LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel ...

  • Page 17

    STM32F103xC, STM32F103xD, STM32F103xE 2.3.10 Boot modes At startup, boot pins are used to select one of three boot options: ● Boot from user Flash: you have an option to boot from any of two memory banks. By default, boot from ...

  • Page 18

    Description 2.3.14 Low-power modes The STM32F103xC, STM32F103xD and STM32F103xE performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ● Sleep mode In Sleep mode, only the CPU ...

  • Page 19

    STM32F103xC, STM32F103xD, STM32F103xE periodic interrupt clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of ...

  • Page 20

    Description General-purpose timers (TIMx) There are synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler ...

  • Page 21

    STM32F103xC, STM32F103xD, STM32F103xE 2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs) The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5). These five interfaces provide asynchronous ...

  • Page 22

    Description 2.3.24 Universal serial bus (USB) The STM32F103xC, STM32F103xD and STM32F103xE performance line embed a USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting ...

  • Page 23

    STM32F103xC, STM32F103xD, STM32F103xE This dual digital Interface supports the following features: ● two DAC converters: one for each output channel ● 8-bit or 12-bit monotonic output ● left or right data alignment in 12-bit mode ● synchronized update capability ● ...

  • Page 24

    Pinouts and pin descriptions 3 Pinouts and pin descriptions Figure 3. STM32F103xC and STM32F103xE performance line BGA144 ballout PC13- PE3 PE2 A TAMPER-RTC PC14- B PE4 PE5 OSC32_IN PC15 BAT PF0 OSC32_OUT D OSC_IN V ...

  • Page 25

    STM32F103xC, STM32F103xD, STM32F103xE Figure 4. STM32F103xC and STM32F103xE performance line BGA100 ballout 1 2 PC14- PC13- A PE2 OSC32_IN TAMPER-RTC PC15 BAT PE3 OSC32_OUT C OSC_IN V SS_5 PE4 D OSC_OUT V DD_5 PE5 E NRST PE6 PC2 ...

  • Page 26

    Pinouts and pin descriptions Figure 5. STM32F103xC and STM32F103xE performance line LQFP144 pinout PE2 1 PE3 2 PE4 3 PE5 4 PE6 5 VBAT 6 PC13-TAMPER-RTC 7 PC14-OSC32_IN 8 PC15-OSC32_OUT 9 PF0 10 PF1 11 PF2 12 PF3 13 PF4 ...

  • Page 27

    STM32F103xC, STM32F103xD, STM32F103xE Figure 6. STM32F103xC and STM32F103xE performance line LQFP100 pinout VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST VSSA VREF- VREF+ VDDA PA0-WKUP PE2 1 PE3 2 PE4 3 PE5 4 PE6 ...

  • Page 28

    Pinouts and pin descriptions Figure 7. STM32F103xC and STM32F103xE performance line LQFP64 pinout PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT 28/130 STM32F103xC, STM32F103xD, STM32F103xE VBAT ...

  • Page 29

    STM32F103xC, STM32F103xD, STM32F103xE Figure 8. STM32F103xC and STM32F103xE performance line WLCSP64 ballout, ball side PC14 C PC13 D OSC_IN OSC_OUT E F PC1 BOOT0 PB5 DD_3 SS_3 PC15 PB9 ...

  • Page 30

    Pinouts and pin descriptions Table 5. High-density STM32F103xx pin definitions Pins Pin name ...

  • Page 31

    STM32F103xC, STM32F103xD, STM32F103xE Table 5. High-density STM32F103xx pin definitions (continued) Pins Pin name ( PA0-WKUP K2 ...

  • Page 32

    Pinouts and pin descriptions Table 5. High-density STM32F103xx pin definitions (continued) Pins Pin name ...

  • Page 33

    STM32F103xC, STM32F103xD, STM32F103xE Table 5. High-density STM32F103xx pin definitions (continued) Pins Pin name L10 K10 - - 59 81 K10 J10 - - ...

  • Page 34

    Pinouts and pin descriptions Table 5. High-density STM32F103xx pin definitions (continued) Pins Pin name A12 A10 105 C11 106 107 108 A11 A9 ...

  • Page 35

    ... This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 9. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins ...

  • Page 36

    Pinouts and pin descriptions Table 6. FSMC pin definition Pins CF PE2 PE3 PE4 PE5 PE6 PF0 A0 PF1 A1 PF2 A2 PF3 A3 PF4 A4 PF5 A5 PF6 NIORD PF7 NREG PF8 NIOWR PF9 CD PF10 INTR PF11 NIOS16 ...

  • Page 37

    STM32F103xC, STM32F103xD, STM32F103xE Table 6. FSMC pin definition (continued) Pins CF PD9 D14 PD10 D15 PD11 PD12 PD13 PD14 D0 PD15 D1 PG2 PG3 PG4 PG5 PG6 PG7 PD0 D2 PD1 D3 PD3 PD4 NOE PD5 NWE PD6 NWAIT PD7 ...

  • Page 38

    Memory mapping 4 Memory mapping The memory map is shown in Figure 9. Memory map 0xFFFF FFFF 0xE000 0000 0xDFFF FFFF 0xC000 0000 0xBFFF FFFF 0xA000 0000 0x9FFF FFFF 0x8000 0000 0x7FFF FFFF 0x6000 0000 0x5FFF FFFF 0x4000 0000 0x3FFF ...

  • Page 39

    STM32F103xC, STM32F103xD, STM32F103xE 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, ...

  • Page 40

    Electrical characteristics 5.1.6 Power supply scheme Figure 12. Power supply scheme Caution: In Figure 12, the 4.7 µF capacitor must be connected to V 5.1.7 Current consumption measurement Figure 13. Current consumption measurement scheme 40/130 STM32F103xC, STM32F103xD, STM32F103xE DD3 I ...

  • Page 41

    STM32F103xC, STM32F103xD, STM32F103xE 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 8: Current characteristics, and damage to the device. These are stress ratings only and functional operation of the device at these conditions is not ...

  • Page 42

    Electrical characteristics Table 9. Thermal characteristics Symbol T STG T J 5.3 Operating conditions 5.3.1 General operating conditions Table 10. General operating conditions Symbol f Internal AHB clock frequency HCLK f Internal APB1 clock frequency PCLK1 f Internal APB2 clock ...

  • Page 43

    STM32F103xC, STM32F103xD, STM32F103xE 5.3.2 Operating conditions at power-up / power-down The parameters given in temperature condition summarized in Table 11. Operating conditions at power-up / power-down Symbol V rise time rate DD t VDD V fall time rate DD 5.3.3 ...

  • Page 44

    Electrical characteristics 5.3.4 Embedded reference voltage The parameters given in temperature and V Table 13. Embedded internal reference voltage Symbol V Internal reference voltage REFINT ADC sampling time when (1) T reading the internal reference S_vrefint voltage Internal reference voltage ...

  • Page 45

    STM32F103xC, STM32F103xD, STM32F103xE Table 14. Maximum current consumption in Run mode, code with data processing running from Flash Symbol Parameter Supply current Run mode 1. Based on characterization, not tested in production. 2. External clock is 8 ...

  • Page 46

    Electrical characteristics Figure 14. Typical current consumption in Run mode versus frequency (at 3 code with data processing running from RAM, peripherals enabled -45 Figure 15. Typical current consumption in ...

  • Page 47

    STM32F103xC, STM32F103xD, STM32F103xE Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM Symbol Parameter Supply current Sleep mode 1. Based on characterization, tested in production External clock is 8 ...

  • Page 48

    Electrical characteristics Table 17. Typical and maximum current consumptions in Stop and Standby modes Symbol Parameter Regulator in run mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Supply current in Stop mode Regulator in ...

  • Page 49

    STM32F103xC, STM32F103xD, STM32F103xE Figure 17. Typical current consumption in Stop mode with regulator in run mode versus temperature at different V 700 600 500 400 300 200 100 0 DD -45 25 Temperature (°C) Doc ID 14611 Rev 8 Electrical ...

  • Page 50

    Electrical characteristics Figure 18. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different V 700 600 500 400 300 200 100 0 -45 50/130 STM32F103xC, STM32F103xD, STM32F103xE values Temperature (°C) Doc ...

  • Page 51

    STM32F103xC, STM32F103xD, STM32F103xE Figure 19. Typical current consumption in Standby mode versus temperature at different V 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -45 values Temperature (°C) Doc ID 14611 Rev 8 Electrical characteristics ...

  • Page 52

    Electrical characteristics Typical current consumption The MCU is placed under the following conditions: ● All I/O pins are in input mode with a static value at V ● All peripherals are disabled except explicitly mentioned. ● The ...

  • Page 53

    STM32F103xC, STM32F103xD, STM32F103xE Table 19. Typical current consumption in Sleep mode, code running from Flash or RAM Symbol Parameter Supply I current in DD Sleep mode 1. Typical values are measures Add an additional power consumption of ...

  • Page 54

    Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in under the following conditions: ● all I/O pins are in input mode with a static value at V ● all peripherals are disabled unless ...

  • Page 55

    STM32F103xC, STM32F103xD, STM32F103xE Table 20. Peripheral current consumption Peripheral APB2 MHz, f HCLK 2. Specific conditions for ADC the ADC_CR2 register is set to 1. 5.3.6 External clock source characteristics High-speed external user clock ...

  • Page 56

    Electrical characteristics Low-speed external user clock generated from an external source The characteristics given in external clock source, and under ambient temperature and supply voltage conditions summarized in Table Table 22. Low-speed external user clock characteristics Symbol User External clock ...

  • Page 57

    STM32F103xC, STM32F103xD, STM32F103xE Figure 21. Low-speed external clock source AC timing diagram V LSEH 90% 10% V LSEL t r(LSE) EXTER NAL CLOCK SOURC E t f(LSE) t W(LSE) T LSE f LSE_ext OSC32_IN Doc ID 14611 Rev 8 Electrical ...

  • Page 58

    Electrical characteristics High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained ...

  • Page 59

    STM32F103xC, STM32F103xD, STM32F103xE Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with ...

  • Page 60

    Electrical characteristics Figure 23. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors 5.3.7 Internal clock source characteristics The parameters given in temperature and V High-speed internal (HSI) RC oscillator Table 25. HSI oscillator ...

  • Page 61

    STM32F103xC, STM32F103xD, STM32F103xE Table 26. LSI oscillator characteristics Symbol (3) t LSI oscillator startup time su(LSI) (3) I LSI oscillator power consumption DD(LSI –40 to 105 °C unless otherwise specified ...

  • Page 62

    Electrical characteristics 5.3.8 PLL characteristics The parameters given in temperature and V Table 28. PLL characteristics Symbol PLL input clock f PLL_IN PLL input clock duty cycle f PLL multiplier output clock PLL_OUT t PLL lock time LOCK Jitter Cycle-to-cycle ...

  • Page 63

    STM32F103xC, STM32F103xD, STM32F103xE Table 30. Flash memory endurance and data retention Symbol Parameter N Endurance END t Data retention RET 1. Based on characterization not tested in production. 2. Cycling performed over the whole temperature range. 5.3.10 FSMC characteristics Asynchronous ...

  • Page 64

    Electrical characteristics Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to ...

  • Page 65

    STM32F103xC, STM32F103xD, STM32F103xE Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings Symbol t FSMC_NEx low to FSMC_NADV low v(NADV_NE) t FSMC_NADV low time w(NADV pF Based on characterisation, not tested in production. Figure 25. Asynchronous ...

  • Page 66

    Electrical characteristics Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings Symbol t FSMC_NEx low to FSMC_NADV low v(NADV_NE) t FSMC_NADV low time w(NADV pF Based on characterisation, not tested in production. Figure 26. Asynchronous multiplexed ...

  • Page 67

    STM32F103xC, STM32F103xD, STM32F103xE Table 33. Asynchronous multiplexed PSRAM/NOR read timings Symbol t FSMC_BL hold time after FSMC_NOE high h(BL_NOE) t FSMC_NEx low to FSMC_BL valid v(BL_NE) t Data to FSMC_NEx high setup time su(Data_NE) t Data to FSMC_NOE high setup ...

  • Page 68

    Electrical characteristics Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms FSMC_NEx FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 34. Asynchronous multiplexed PSRAM/NOR write timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NWE low v(NWE_NE) t FSMC_NWE low ...

  • Page 69

    STM32F103xC, STM32F103xD, STM32F103xE Synchronous waveforms and timings Figure 28 through Table 38 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● BurstAccessMode = FSMC_BurstAccessMode_Enable; ● MemoryType = FSMC_MemoryType_CRAM; ● WriteBurst = ...

  • Page 70

    Electrical characteristics Table 35. Synchronous multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x = 0...2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x = 0...2) d(CLKL-NExH) t FSMC_CLK low to FSMC_NADV low ...

  • Page 71

    STM32F103xC, STM32F103xD, STM32F103xE Figure 29. Synchronous multiplexed PSRAM write timings Doc ID 14611 Rev 8 Electrical characteristics 71/130 ...

  • Page 72

    Electrical characteristics Table 36. Synchronous multiplexed PSRAM write timings Symbol t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-ADV) t d(CLKL-ADIV) t d(CLKL-Data) t su(NWAITV-CLKH) t h(CLKH-NWAITV) t d(CLKL-NBLH) ...

  • Page 73

    STM32F103xC, STM32F103xD, STM32F103xE Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings Table 37. Synchronous non-multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x = 0...2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x = ...

  • Page 74

    Electrical characteristics Figure 31. Synchronous non-multiplexed PSRAM write timings Table 38. Synchronous non-multiplexed PSRAM write timings Symbol t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-Data) t su(NWAITV-CLKH) t ...

  • Page 75

    STM32F103xC, STM32F103xD, STM32F103xE PC Card/CompactFlash controller waveforms and timings Figure 32 through corresponding timings. The results shown in this table are obtained with the following FSMC configuration: ● COM.FSMC_SetupTime = 0x04; ● COM.FSMC_WaitSetupTime = 0x07; ● COM.FSMC_HoldSetupTime = 0x04; ● ...

  • Page 76

    Electrical characteristics Figure 33. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NREG FSMC_NIOWR FSMC_NIORD t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[15:0] 76/130 STM32F103xC, STM32F103xD, STM32F103xE High t v(NCE4_1-A) t d(NREG-NCE4_1) t d(NIORD-NCE4_1) t w(NWE) MEMxHIZ =1 t ...

  • Page 77

    STM32F103xC, STM32F103xD, STM32F103xE Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG FSMC_NWE t d(NCE4_1-NOE) FSMC_NOE (1) FSMC_D[15:0] 1. Only data bits 0...7 are read (bits 8...15 are disregarded). t v(NCE4_1-A) High ...

  • Page 78

    Electrical characteristics Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[7:0](1) 1. Only data bits 0...7 are driven (bits 8...15 remains HiZ). Figure 36. PC Card/CompactFlash controller ...

  • Page 79

    STM32F103xC, STM32F103xD, STM32F103xE Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access FSMC_NIOWR FSMC_A[10:0] FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIORD t d(NCE4_1-NIOWR) FSMC_NIOWR FSMC_D[15:0] Table 39. Switching characteristics for PC Card/CF read and write cycles Symbol FSMC_NCEx low (x = ...

  • Page 80

    Electrical characteristics Table 39. Switching characteristics for PC Card/CF read and write cycles Symbol t FSMC_NIOWR low width w(NIOWR) t FSMC_NIOWR low to FSMC_D[15:0] valid v(NIOWR-D) t FSMC_NIOWR high to FSMC_D[15:0] invalid h(NIOWR-D) t FSMC_NCE4_1 low to FSMC_NIOWR valid d(NCE4_1-NIOWR) ...

  • Page 81

    STM32F103xC, STM32F103xD, STM32F103xE Figure 38. NAND controller waveforms for read access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE (NRE) FSMC_D[15:0] Figure 39. NAND controller waveforms for write access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE (NRE) FSMC_D[15:0] Figure 40. NAND ...

  • Page 82

    Electrical characteristics Figure 41. NAND controller waveforms for common memory write access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE FSMC_D[15:0] Table 40. Switching characteristics for NAND Flash read and write cycles Symbol (2) t FSMC_D[15:0] valid before FSMC_NWE high d(D-NWE) ...

  • Page 83

    STM32F103xC, STM32F103xD, STM32F103xE 5.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed ...

  • Page 84

    Electrical characteristics Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD ...

  • Page 85

    STM32F103xC, STM32F103xD, STM32F103xE Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: ● A supply overvoltage is applied to each power supply pin ● A current injection is applied to each input, output ...

  • Page 86

    Electrical characteristics 5.3.14 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in performed under the conditions summarized in compliant. Table 46. I/O static characteristics Symbol Parameter Standard IO input low level voltage V IL (1) IO ...

  • Page 87

    STM32F103xC, STM32F103xD, STM32F103xE Figure 42. Standard I/O input characteristics - CMOS port Figure 43. Standard I/O input characteristics - TTL port Doc ID 14611 Rev 8 Electrical characteristics 87/130 ...

  • Page 88

    Electrical characteristics Figure 44 tolerant I/O input characteristics - CMOS port Figure 45 tolerant I/O input characteristics - TTL port Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, ...

  • Page 89

    STM32F103xC, STM32F103xD, STM32F103xE Output voltage levels Unless otherwise specified, the parameters given in performed under ambient temperature and V Table 10. All I/Os are CMOS and TTL compliant. Table 47. Output voltage characteristics Symbol Output low level voltage for an ...

  • Page 90

    Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Table 48, respectively. Unless otherwise specified, the parameters given in performed under ambient temperature and V Table 10. Table 48. I/O AC characteristics MODEx[1:0] ...

  • Page 91

    STM32F103xC, STM32F103xD, STM32F103xE Figure 46. I/O AC characteristics definition EXT ERNAL OUTPUT ON 50pF Maximum frequency is achieved ≤ 2/3)T and if the duty cycle is (45-55%) 5.3.15 NRST pin characteristics The NRST ...

  • Page 92

    Electrical characteristics 5.3.16 TIM timer characteristics The parameters given in Refer to Section 5.3.14: I/O port characteristics function characteristics (output compare, input capture, external clock, PWM output). Table 50. TIMx Symbol t Timer resolution time res(TIM) Timer external clock f ...

  • Page 93

    STM32F103xC, STM32F103xD, STM32F103xE 5.3.17 Communications interfaces interface characteristics Unless otherwise specified, the parameters given in performed under ambient temperature, f summarized in Table The STM32F103xC, STM32F103xD and STM32F103xESTM32F103xF and STM32F103xG performance line I protocol with the following ...

  • Page 94

    Electrical characteristics 2 Figure 48 bus AC waveforms and measurement circuit bus S TART SDA t r(SDA) t f(SDA) t h(STA) SCL t w(SCLH) 1. Measurement points are done at CMOS levels: 0.3V Table 52. ...

  • Page 95

    STM32F103xC, STM32F103xD, STM32F103xE SPI characteristics Unless otherwise specified, the parameters given in are derived from tests performed under ambient temperature, f supply voltage conditions summarized in Refer to Section 5.3.14: I/O port characteristics function characteristics (NSS, ...

  • Page 96

    Electrical characteristics Figure 49. SPI timing diagram - slave mode and CPHA = 0 NSS input t SU(NSS) CPHA= 0 CPOL=0 t w(SCKH) CPHA w(SCKL) CPOL=1 t a(SO) MISO OUT su(SI) MOSI I NPUT Figure ...

  • Page 97

    STM32F103xC, STM32F103xD, STM32F103xE Figure 51. SPI timing diagram - master mode High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 t su(MI) MISO INP UT MOSI OUTUT 1. Measurement points are done at CMOS levels: 0.3V ...

  • Page 98

    Electrical characteristics 2 Table 54 characteristics Symbol Parameter I2S slave input clock duty DuCy(SCK) cycle clock frequency 1/t c(CK r(CK clock rise and fall time t f(CK) (1) t ...

  • Page 99

    STM32F103xC, STM32F103xD, STM32F103xE 2 Figure 52 slave timing diagram (Philips protocol) CPOL = 0 CPOL = 1 WS input SD transmit SD receive 1. Measurement points are done at CMOS levels: 0.3 × LSB transmit/receive of ...

  • Page 100

    Electrical characteristics SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in performed under ambient temperature, f summarized in Table Refer to Section 5.3.14: I/O port characteristics function characteristics (D[7:0], CMD, CK). Figure 54. SDIO high-speed ...

  • Page 101

    STM32F103xC, STM32F103xD, STM32F103xE Table 55 MMC characteristics Symbol Clock frequency in data transfer f PP mode t Clock low time, f W(CKL) t Clock high time, f W(CKH) t Clock rise time r t Clock fall time f ...

  • Page 102

    Electrical characteristics Table 57. USB DC electrical characteristics Symbol Input levels V USB operating voltage DD (4) V Differential input sensitivity DI (4) V Differential common mode range Includes V CM (4) V Single ended receiver threshold SE Output levels ...

  • Page 103

    STM32F103xC, STM32F103xD, STM32F103xE 5.3.19 12-bit ADC characteristics Unless otherwise specified, the parameters given in from tests performed under ambient temperature, f conditions summarized in Note recommended to perform a calibration after each power-up. Table 59. ADC characteristics Symbol ...

  • Page 104

    Electrical characteristics Equation 1: R AIN < R ------------------------------------------------------------- - R AIN × ADC The formula above allowed for an error below 1/4 of LSB. Here (from 12-bit resolution). Table 60. R AIN T (cycles) ...

  • Page 105

    STM32F103xC, STM32F103xD, STM32F103xE Table 62. ADC accuracy Symbol ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could ...

  • Page 106

    Electrical characteristics Figure 58. Typical connection diagram using the ADC R AIN (1) V AIN 1. Refer to Table represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the parasitic pad capacitance ...

  • Page 107

    STM32F103xC, STM32F103xD, STM32F103xE Figure 60. Power supply and reference decoupling ( and V REF+ REF– 1 µ inputs are available only on 100-pin packages. Doc ID 14611 Rev 8 Electrical characteristics V ) connected to ...

  • Page 108

    Electrical characteristics 5.3.20 DAC electrical specifications Table 63. DAC characteristics Symbol Parameter V Analog supply voltage DDA V Reference supply voltage REF+ V Ground SSA (1) R Resistive load with buffer ON 5 LOAD Impedance output with buffer (1) R ...

  • Page 109

    STM32F103xC, STM32F103xD, STM32F103xE Table 63. DAC characteristics (continued) Symbol Parameter Offset error (difference between (2) Offset measured value at Code (0x800) and the ideal value = V /2) REF+ Gain Gain error (2) error Settling time (full scale: for a ...

  • Page 110

    Electrical characteristics 5.3.21 Temperature sensor characteristics Table 64. TS characteristics Symbol SENSE Avg_Slope Average slope V Voltage at 25 °C 25 (1) t Startup time START ADC sampling time when reading the (2)(1) T S_temp temperature 1. ...

  • Page 111

    STM32F103xC, STM32F103xD, STM32F103xE 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product ...

  • Page 112

    Package characteristics Figure 62. BGA pad footprint Table 65. Recommended PCB design rules (0.80/0.75 mm pitch BGA) Dimension Dpad Dsm Solder paste – Non solder mask defined pads are recommended – mils screen print 112/130 STM32F103xC, STM32F103xD, ...

  • Page 113

    STM32F103xC, STM32F103xD, STM32F103xE Figure 63. LFBGA144 – 144-ball low profile fine pitch ball grid array mm, 0.8 mm pitch, package outline 1. Drawing is not to scale. Table 66. LFBGA144 – 144-ball low profile fine pitch ball ...

  • Page 114

    Package characteristics Figure 64. LFBGA100 - low profile fine pitch ball grid array package outline 1. Drawing is not to scale. Table 67. LFBGA100 - low profile fine pitch ball grid array ...

  • Page 115

    STM32F103xC, STM32F103xD, STM32F103xE Figure 65. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline A1 ball corner H Marking area Wafer back side Ball eee 1. Drawing is not to scale. 2. Primary datum Z and ...

  • Page 116

    Package characteristics Figure 66. BGA pad footprint Table 69. Recommended PCB design rules (0.5mm pitch BGA) Dimension Dpad Dsm PCD pad size – Non solder mask defined – Micro via under bump allowed 116/130 STM32F103xC, STM32F103xD, STM32F103xE Recommended values ∅ ...

  • Page 117

    STM32F103xC, STM32F103xD, STM32F103xE Figure 67. LQFP144 mm, 144-pin low-profile quad flat package outline Seating plane ccc 108 109 144 Pin 1 1 identification 1. Drawing is not to ...

  • Page 118

    Package characteristics Figure 69. LQFP100 100-pin low-profile quad flat package outline 100 26 Pin identification e 1. Drawing is not to scale. 2. Dimensions are in ...

  • Page 119

    STM32F103xC, STM32F103xD, STM32F103xE Figure 71. LQFP64 – pin low-profile quad flat package outline Pin 1 identification Drawing is not to scale. 2. ...

  • Page 120

    Package characteristics 6.2 Thermal characteristics The maximum chip junction temperature (T Table 10: General operating conditions on page The maximum chip-junction temperature, T using the following equation: Where: ● T max is the maximum ambient temperature in °C, A Θ ...

  • Page 121

    STM32F103xC, STM32F103xD, STM32F103xE 6.2.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, ...

  • Page 122

    Package characteristics Using the values obtained in – For LQFP100, 46 °C 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C Jmax This is within the range of the suffix ...

  • Page 123

    STM32F103xC, STM32F103xD, STM32F103xE 7 Part numbering Table 74. Ordering information scheme Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 103 = performance line Pin count pins V = 100 pins ...

  • Page 124

    Revision history 8 Revision history Table 75. Document revision history Date Revision 07-Apr-2008 22-May-2008 124/130 STM32F103xC, STM32F103xD, STM32F103xE 1 Initial release. Document status promoted from Target Specification to Preliminary Data. Section 1: Introduction and the family modified. Small text changes. ...

  • Page 125

    STM32F103xC, STM32F103xD, STM32F103xE Table 75. Document revision history Date Revision 21-Jul-2008 Document status promoted from Preliminary Data to full datasheet. FSMC (flexible static memory controller) on page 15 Number of complementary channels corrected in STM32F103xC, STM32F103xD and STM32F103xE performance line ...

  • Page 126

    Revision history Table 75. Document revision history Date Revision 12-Dec-2008 126/130 STM32F103xC, STM32F103xD, STM32F103xE Timers specified on page 1 Section 2.2: Full compatibility throughout the family Table 4: High-density timer feature comparison General-purpose timers (TIMx) TIM8) on page 19 updated. ...

  • Page 127

    STM32F103xC, STM32F103xD, STM32F103xE Table 75. Document revision history Date Revision 30-Mar-2009 I/O information clarified on page STM32F103xE performance line BGA100 ballout I/O information clarified on page In Table 5: High-density STM32F103xx pin – I/O level of pins PF11, PF12, PF13, ...

  • Page 128

    Revision history Table 75. Document revision history Date Revision 21-Jul-2009 24-Sep-2009 128/130 STM32F103xC, STM32F103xD, STM32F103xE Figure 1: STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram Note 5 updated and Note 4 STM32F103xx pin definitions. V and T added to RERINT ...

  • Page 129

    STM32F103xC, STM32F103xD, STM32F103xE Table 75. Document revision history Date Revision 19-Apr-2011 Updated package choice for 103Rx in Updated footnotes below and Table 8: Current characteristics on page 41 Updated tw min in Table 21: High-speed external user clock characteristics on ...

  • Page 130

    ... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...