STM32L151VC STMicroelectronics, STM32L151VC Datasheet - Page 15

• Manufacturer Part Number: STM32L151VC
• Description: Ultra-low-power ARM Cortex-M3 MCU with 256 Kbytes Flash, 32 MHz CPU, LCD, USB, 3xOp-amp
• Manufacturer: STMicroelectronics

Specifications of STM32L151VC

• Operating Power Supply Range: 1.65 V to 3.6 V (without BOR) or 1.8 V to 3.6 V
• 7 Modes: Sleep, Low-power run (11 μA at 32 kHz) , Low-power sleep (4.4 μA), Stop with RTC, Stop (650 nA), Standby with RTC, Standby (300 nA)
• Ultralow Leakage Per I/o: 50 nA max
• Fast Wakeup Time From Stop: 8 μs
• Core: ARM 32-bit Cortex™-M3 CPU
• Dma: 12-channel DMA controller
• 11 Timers: one 32-bit and six 16-bit general-purpose timers, two 16-bit basic timers, two watchdog timers (independent and window)

STM32L151xC, STM32L152xC
3.3
3.3.1
3.3.2
Nested vectored interrupt controller (NVIC)
The ultralow power STM32L15xxC embeds a nested vectored interrupt controller able to
handle up to 53 maskable interrupt channels (not including the 16 interrupt lines of
Cortex™-M3) and 16 priority levels.
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This hardware block provides flexible interrupt management features with minimal interrupt
latency.
Reset and supply management
Power supply schemes
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Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
The device exists in two versions:
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As the BOR can be activated and deactivated at run time, this distinction is important only
for power-up phase.
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
power ramp-up should guarantee that 1.65 V is reached on V
the POR area.
After the V
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable BOR permanently: in this case, the V
1.65 V.
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
V
externally through V
V
and PLL (minimum voltage to be applied to V
V
The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
The other version without BOR at power up operates between 1.65 V and 3.6 V.
DD
SSA
DDA
= 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
, V
DD
and V
DDA
threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
SSA
= 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
must be connected to V
DD
pins.
Doc ID 022799 Rev 1
DD
and V
DDA
SS
is 1.8 V when the ADC is used).
, respectively.
DD
DD
min value at power down is
at least 1 ms after it exits
Functional overview
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