ST7260E1 STMicroelectronics, ST7260E1 Datasheet - Page 25

• Manufacturer Part Number: ST7260E1
• Description: LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 8K FLASH/ROM AND SERIAL COMMUNICATION INTERFACE (SCI)
• Manufacturer: STMicroelectronics

Specifications of ST7260E1

• 4 Or 8 Kbytes Program Memory: high density Flash (HDFlash), or FastROM with readout and write protection

ST7260xx
7
7.1
Caution:
7.2
7.2.1
7.2.2
Reset and clock management
Reset
The Reset procedure is used to provide an orderly software start-up or to exit low power
modes.
Three reset modes are provided: a low voltage (LVD) reset, a watchdog reset and an
external reset at the RESET pin.
A reset causes the reset vector to be fetched from addresses FFFEh and FFFFh in order to
be loaded into the PC and with program execution starting from this point.
An internal circuitry provides a 4096 CPU clock cycle delay from the time that the oscillator
becomes active.
When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior
Low voltage detector (LVD)
Low voltage reset circuitry generates a reset when V
●
●
During low voltage reset, the RESET pin is held low, thus permitting the MCU to reset other
devices.
It is recommended to make sure that the V
device is exiting from Reset, to ensure the application functions properly.
Watchdog reset
When a watchdog reset occurs, the RESET pin is pulled low permitting the MCU to reset
other devices in the same way as the low voltage reset
External reset
The external reset is an active low input signal applied to the RESET pin of the MCU.
As shown in
CPU clock cycles.
An internal Schmitt trigger at the RESET pin is provided to improve noise immunity.
below V
below V
IT+
IT-
Figure
when V
when V
12, the RESET signal must stay low for a minimum of one and a half
DD
DD
is falling.
is rising,
DD
supply voltage rises monotonously when the
DD
(Figure
is:
Reset and clock management
9).
25/139