ST7260E1 STMicroelectronics, ST7260E1 Datasheet - Page 86

• Manufacturer Part Number: ST7260E1
• Description: LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 8K FLASH/ROM AND SERIAL COMMUNICATION INTERFACE (SCI)
• Manufacturer: STMicroelectronics

Specifications of ST7260E1

• 4 Or 8 Kbytes Program Memory: high density Flash (HDFlash), or FastROM with readout and write protection

Serial communications interface (SCI)
13.3.4
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Table 40.
Data register (SCIDR)
Contains the Received or Transmitted data character, depending on whether it is read from
or written to.
The Data register performs a double function (read and write) since it is composed of two
registers, one for transmission (TDR) and one for reception (RDR).
The TDR register provides the parallel interface between the internal bus and the output
shift register (see
The RDR register provides the parallel interface between the input shift register and the
internal bus (see
SCIDR
Bit
3
2
1
0
DR7
R/W
7
Name
RWU
SBK
RE
TE
SCICR2 register description (continued)
Transmitter Enable
Receiver Enable
Receiver Wake-Up
Send Break
DR6
R/W
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Notes:
- During transmission, a ‘0’ pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble
(Idle line) after the current word.
- When TE is set there is a 1 bit-time delay before the transmission starts.
Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits
are both cleared (or if TE is never set).
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
Note: Before selecting Mute mode (setting the RWU bit), the SCI must first receive
some data, otherwise it cannot function in Mute mode with Wake-Up by Idle line
detection.
This bit determines if the SCI is in mute mode or not. It is set and cleared by
software and can be cleared by hardware when a wake-up sequence is recognized.
0: Receiver in Active mode
1: Receiver in Mute mode
This bit set is used to send break characters. It is set and cleared by software.
0: No break character is transmitted.
1: Break characters are transmitted.
Note: If the SBK bit is set to ‘1’ and then to ‘0’, the transmitter will send a Break word
at the end of the current word.
6
Figure
Figure
38).
38).
DR5
R/W
5
DR4
R/W
4
Function
DR3
R/W
3
DR2
R/W
2
Reset value:
DR1
R/W
1
undefined (xxh)
ST7260xx
DR0
R/W
0