ST7260E1 STMicroelectronics, ST7260E1 Datasheet - Page 94

• Manufacturer Part Number: ST7260E1
• Description: LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 8K FLASH/ROM AND SERIAL COMMUNICATION INTERFACE (SCI)
• Manufacturer: STMicroelectronics

Specifications of ST7260E1

• 4 Or 8 Kbytes Program Memory: high density Flash (HDFlash), or FastROM with readout and write protection

USB interface (USB)
14.4.6
Note:
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Control register (CTLR)
Bits 7:4 = Reserved. Forced by hardware to 0.
Bit 3 = RESUME Resume.
This bit is set by software to wake-up the Host when the ST7 is in suspend mode.
0: Resume signal not forced
1: Resume signal forced on the USB bus.
Software should clear this bit after the appropriate delay.
Bit 2 = PDWN Power down.
This bit is set by software to turn off the 3.3V on-chip voltage regulator that supplies the
external pull-up resistor and the transceiver.
0: Voltage regulator on
1: Voltage regulator off
After turning on the voltage regulator, software should allow at least 3 µs for stabilisation of
the power supply before using the USB interface.
Bit 1 = FSUSP Force suspend mode.
This bit is set by software to enter Suspend mode. The ST7 should also be halted allowing
at least 600 ns before issuing the HALT instruction.
0: Suspend mode inactive
1: Suspend mode active
When the hardware detects USB activity, it resets this bit (it can also be reset by software).
Bit 0 = FRES Force reset.
This bit is set by software to force a reset of the USB interface, just as if a RESET sequence
came from the USB.
0: Reset not forced
1: USB interface reset forced.
The USB is held in RESET state until software clears this bit, at which point a “USB-RESET”
interrupt will be generated if enabled.
CTLR
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
RESUME
R/W
3
PDWN
R/W
2
Reset value:
FSUSP
R/W
1
0000 0110 (06h)
ST7260xx
FRES
R/W
0