ST92124V1Q-Auto STMicroelectronics, ST92124V1Q-Auto Datasheet - Page 173

• Manufacturer Part Number: ST92124V1Q-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST92124V1Q-Auto

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

EXTENDED FUNCTION TIMER (Cont’d)
10.3.3.4 Output Compare
In this section, the index, i, may be 1 or 2.
This function can be used to control an output
waveform or indicating when a period of time has
elapsed.
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the free run-
ning counter each timer clock cycle.
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OC
Timing resolution is one count of the free running
counter: (
Procedure
To use the output compare function, select the fol-
lowing in the CR2 register:
– Set the OCiE bit if an output is needed, the OC-
– Select the timer clock (CC[1:0] see
Select the following in the CR1/CR3 register:
– Select the OLVLi bit to be applied to the OCMP
– To enable both OCMP1 & OCMP2 interrupts, set
When a match is found:
– The OCFi bit is set.
– The OCMPi pin takes the OLVLi bit value (the
MPi pin is then dedicated to the output compare
function.
pins after the match occurs.
the OCIE bit in the CR1 register (in this case, the
OC1IE & OC2IE enable bits are not significant).
To enable only one OCMP interrupt, reset the
OCIE bit and set the OC1IE (or OC2IE) bit.
Note: If OCIE is reset and both OC1IE & OC2IE
are set, both interrupts are enabled.
In all cases, set the EFTIS bit to enable timer in-
terrupts globally.
OCMPi pin latch is forced low during reset and
stays low until a valid compare changes it to the
OLVLi level).
– Assigns pins with a programmable value if the
– Sets a flag in the status register
– Generates an interrupt if enabled
OCiR
OCiE bit is set
INTCLK /
i
R value to 8000h.
CC[1:0]
MS Byte
OCiHR
).
LS Byte
OCiLR
Table
36).
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
– A timer interrupt is generated under the following
Clearing the output compare interrupt request is
done by:
– An access (read or write) to the SR register while
– An access (read or write) to the OCiLR register.
Note: After a write access to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
If the OCiE bit is not set, the OCMPi pin is a gen-
eral I/O port and the OLVLi bit will not appear
when match is found but an interrupt could be gen-
erated if the OCIE bit is set.
The value in the 16-bit OC
OLVLi bit should be changed after each success-
ful comparison in order to control an output wave-
form or establish a new elapsed timeout.
The OC
ing application can be calculated using the follow-
ing formula:
Where:
∆
INTCLK
CC[1:0]
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OC
– Write to the OCiHR register (further compares
– Read the SR register (first step of the clearance
– Write to the OCiLR register (enables the output
t
two conditions :
the OCFi bit is set.
are inhibited).
of the OCFi bit, which may be already set).
compare function and clears the OCFi bit).
1. If the OCIE bit (for both OCMP1 & OCMP2)
2. If the OCIE bit is reset and the OC1IE and /or
and the EFTIS bit are set.
Note: If the OCIE bit is set, the status of the
OC1IE/OC2IE bits in the CR3 register is not
significant.
OC2IE bits are set and the EFTIS bit is set.
Otherwise, the interrupt remains pending until
the related enable bits are set.
i
R register value required for a specific tim-
= Desired output compare period (in
= Internal clock frequency
= Timer clock prescaler
seconds)
∆
OCiR =
(CC1.CC0)
∆t
*
i
R register and the
INTCLK
i
R register:
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