ST92124V1Q-Auto STMicroelectronics, ST92124V1Q-Auto Datasheet - Page 58

• Manufacturer Part Number: ST92124V1Q-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST92124V1Q-Auto

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
REGISTER DESCRIPTION (Cont’d)
Bit 2 = WFIS: Wait For Interrupt Status.
If this bit is reset, the WFI instruction puts the
Flash macrocell in Stand-by mode (immediate
read possible, but higher consumption: 100 µA); if
it is set, the WFI instruction puts the Flash macro-
cell in Power-Down mode (recovery time of 10µs
needed before reading, but lower consumption:
10µA). The Stand-by mode or the Power-Down
mode will be entered only at the end of any current
Flash or
In the same way following an HALT or a STOP in-
struction, the Memory enters Power-Down mode
only after the completion of any current write oper-
ation.
0: Flash in Stand-by mode on WFI
1: Flash in Power-Down mode on WFI
Note: HALT or STOP mode can be exited without
problems, but the user should take care when ex-
iting WFI Power Down mode. If WFIS is set, the
user code must reset the XT_DIV16 bit in the
R242 register (page 55) before executing the WFI
instruction. When exiting WFI mode, this gives the
Flash enough time to wake up before the interrupt
vector fetch.
Bit 1 = FEIEN: Flash &
This bit selects the source of interrupt channel
INTx between the external interrupt pin and the
Flash/
terrupt chapter for the channel number.
0: External interrupt enabled
1: Flash &
Bit 0 = EBUSY:
This bit is automatically set during a Page Update
operation when the first address to be modified is
latched in the
operation when bit EWMS is set. At the end of the
write operation or during a Sector Erase Suspend
this bit is automatically reset and the memory re-
turns to read mode. When this bit is set every read
access to the
(FFh equivalent to a NOP instruction), while every
write access to the
At the end of the write operation this bit is automat-
ically reset and the memory returns to read mode.
Bit EBUSY remains high for a maximum of 10ms
after Power-Up and when exiting Power-Down
mode, meaning that the
ready to be accessed.
58/430
9
E
3 TM
E
3 TM
E
End of Write interrupt. Refer to the In-
3 TM
E
E
write operation.
3 TM
3 TM
E
Interrupt enabled
3 TM
memory will output invalid data
memory, or during Chip Erase
E
3 TM
Busy (Read Only).
E
3 TM
E
memory will be ignored.
3 TM
Interrupt enable.
memory is not yet
0:
1:
3.3.2 Status Registers
Two Status Registers (FESR[1:0] are available to
check the status of the current write operation in
Flash and
During a Flash or an
tempt to read the memory under modification will
output invalid data (FFh equivalent to a NOP in-
struction). This means that the Flash memory is
not fetchable when a write operation is active: the
write operation commands must be given from an-
other memory (
memory).
FLASH &
Address: 224002h /221002h -Read/Write
Reset value: 0000 0000 (00h)
Bit 7 = FEERR: Flash or
Write).
This bit is set by hardware when an error occurs
during a Flash or an
be cleared by software.
0: Write OK
1: Flash or
Bit 6:0 = FESS[6:0]. Flash and
tus Bits (Read Only).
These bits are set by hardware and give the status
of the 7 Flash and
– FESS6 = TestFlash and OTP
– FESS5:4 =
For 128K and 64K Flash devices:
– FESS3:0 = Flash sectors (F3:0)
For the ST92250-Auto (256K):
– FESS3 gives the status of F5, F4 and F3 sectors:
– FESS2:0 = Flash sectors (F2:0)
FEERR FESS6 FESS5 FESS4 FESS3 FESS2 FESS1 FESS0
the status of all these three sectors are ORed on
this bit
E
E
7
3 TM
3 TM
not busy
busy
6
E
E
E
3 TM
3 TM
3 TM
E
3 TM
5
STATUS REGISTER 0 (FESR0)
memories.
E
write error
3 TM
E
sectors
3 TM
E
E
, internal RAM, or external
4
3 TM
3 TM
sectors.
E
3 TM
write operation. It must
write operation any at-
3
write ERRor (Read/
E
3 TM
2
Sectors Sta-
1
0