BTS 6480SF Infineon Technologies, BTS 6480SF Datasheet - Page 59

• Manufacturer Part Number: BTS 6480SF
• Manufacturer: Infineon Technologies

Specifications of BTS 6480SF

• Packages: PG-DSO-36
• Channels: 4.0
• Channel Mix: 2*4,5mohm+2*11mohm
• Led Mode: Yes
• Cranking Mode: No
• Pwm Engine Integrated: Yes

10
The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO,
SI, SCLK and CS. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of CS
indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on
line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter
ensures that data is taken only, when a multiple of 8 bit has been transferred, while the minimum of 16 bit is also
taken into consideration. Therefore the interface provides daisy chain capability even with 8 bit SPI devices.
Figure 25
10.1
CS - Chip Select:
The system micro controller selects the SPOC - BTS6480SF by means of the CS pin. Whenever the pin is in low
state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and
SO is forced into a high impedance state.
CS High to Low transition:
•
•
Figure 26
CS Low to High transition:
•
•
Data Sheet
The requested information is transferred into the shift register.
SO changes from high impedance state to high or low state depending on the logic OR combination between
the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration,
a high signal indicates a faulty transmission. This information stays available to the first rising edge of SCLK.
Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight SCLK
signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the
command is ignored.
Data from shift register is transferred into the addressed register.
SCLK
SO
CS
time
SI
Serial Peripheral Interface (SPI)
Serial Peripheral Interface
SPI Signal Description
Combinatorial Logic for TER Flag
MSB
SI
MSB
14
14
13
13
SI
SCLK
TER
CS
S
12
12
SPI
OR
11
11
SO
S
10
10
1
0
9
9
59
8
8
SO
7
7
6
6
5
5
4
4
Serial Peripheral Interface (SPI)
3
3
TER.emf
SPOC - BTS6480SF
2
2
Rev. 1.0, 2010-04-12
1
1
SPI_16bit .emf
LSB
LSB