BTS 6480SF Infineon Technologies, BTS 6480SF Datasheet - Page 60

• Manufacturer Part Number: BTS 6480SF
• Manufacturer: Infineon Technologies

Specifications of BTS 6480SF

• Packages: PG-DSO-36
• Channels: 4.0
• Channel Mix: 2*4,5mohm+2*11mohm
• Led Mode: Yes
• Cranking Mode: No
• Pwm Engine Integrated: Yes

SCLK - Serial Clock:
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling
edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock.
It is essential that the SCLK pin is in low state whenever chip select CS makes any transition.
SI - Serial Input:
Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling edge
of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to
further information.
SO Serial Output:
Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin
goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to
Section 10.5
10.2
The SPI of SPOC - BTS6480SF provides daisy chain capability. In this configuration several devices are activated
by the same CS signal MCS. The SI line of one device is connected with the SO line of another device (see
Figure
device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the
SCLK line of each device in the chain.
Figure 27
In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The
bit shifted out occurs at the SO pin. After eight SCLK cycles, the data transfer for one device has been finished.
In single chip configuration, the CS line must turn high to make the device accept the transferred data. In daisy
chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using three devices in
daisy chain, three times 16 (or e.g. 16 + 8 +16) bits have to be shifted through the devices. After that, the MCS
line must turn high (see
Data Sheet
MCLK
27), in order to build a chain. The ends of the chain are connected with the output and input of the master
MCS
MO
MI
Daisy Chain Capability
Daisy Chain Configuration
for further information.
SI
Figure
device 1
SPI
28).
SO
SI
60
device 2
SPI
SO
SI
Serial Peripheral Interface (SPI)
device 3
SPOC - BTS6480SF
SPI
Rev. 1.0, 2010-04-12
SPI_DaisyChain .emf
Section 10.5
SO
for