A43E16161V AMIC Technology, Corp., A43E16161V Datasheet - Page 10

• Manufacturer Part Number: A43E16161V
• Description: 1M x 16-Bit x 2 Banks Low Power Synchronous DRAM
• Manufacturer: AMIC Technology, Corp.

Mode Register Filed Table to Program Modes
Register Programmed with MRS
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.
Extended Mode Register Table
Note: BA must be 1 to select the Extended Mode Register (vs. the Mode Register)
PRELIMINARY
A9
A8
0
1
Address
0
0
1
1
A6
Function
0
0
1
1
BA
↓
1
(Note)
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
A7
3. BA must be 0,0 to select the Mode Register (vs. the Extended Mode Register).
Write Burst Length
0
1
0
1
A5
0
1
0
1
Driver Strength
All have to be set to “0”
A10
Test Mode
↓
Mode Register Set
Single Bit
Length
Driver Strength
BA
Burst
(Note 3)
0
(August, 2005, Version 0.0)
Vendor
Type
A9
Only
↓
Use
Full
3/4
1/2
1/4
Driver Strength
RFU
A10
A8
↓
(Note 1)
Up/Down
A6
0
0
0
0
1
1
1
1
Bank
A7
↓
W.B.L
A5
A9
0
0
1
1
0
0
1
1
CAS Latency
(Note 2)
A4
0
1
0
1
0
1
0
1
A6
↓
DS
A8
Reserved
Reserved
Reserved
Reserved
Reserved
Latency
A5
TM
↓
2
3
-
A7
9
A7
0
0
0
0
0
1
1
1
1
1
A4
↓
A3
0
1
Burst Type
0
A6
A2
Sequential
0
0
0
0
1
0
0
0
0
1
Interleave
A3
↓
CAS Latency
Type
A5
Partial-Array Self Refresh:
A1
X
X
A2
0
0
1
1
0
0
1
1
↓
A2
0
0
0
0
1
1
1
1
A4
PASR
AMIC Technology, Corp.
A1
↓
A0
X
X
A1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
A3
BT
A0
0
1
0
1
0
1
0
1
Banks to be Self-Refreshed
Burst Length
A0
↓
All banks (Bank 0, 1)
All banks (Bank 0, 1)
Reserved
Reserved
Reserved
512(Full)
One bank (Bank 1)
BT=0
A2
Address Bus (Ax)
1
2
4
8
A43E16161
Reserved
Reserved
Reserved
Burst Length
Reserved
Reserved
Reserved
Bank 0
A1
Reserved
Reserved
Reserved
Reserved
BT=1
1
2
4
8
A0