A43E16161V AMIC Technology, Corp., A43E16161V Datasheet - Page 30

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A43E16161V

Manufacturer Part Number
A43E16161V
Description
1M x 16-Bit x 2 Banks Low Power Synchronous DRAM
Manufacturer
AMIC Technology, Corp.
Datasheet
CLOCK
A10/AP
ADDR
PRELIMINARY
Read & Write Cycle with Auto Precharge I @Burst Length=4
(CL=2)
(CL=3)
CKE
RAS
CAS
DQM
CS
DQ
DQ
BA
WE
0
Row Active
(A-Bank)
*Note : tRCD should be controlled to meet minimum tRAS before internal precharge start.
RAa
RAa
1
(In the case of Burst Length=1 & 2, BRSW mode)
(August, 2005, Version 0.0)
2
3
Row Active
(B-Bank)
RBb
RBb
4
Auto Precharge
Read with
(A-Bank)
CAa
5
6
QAa0
7
QAa1
QAa0
Auto Precharge
8
Start Point
(A-Bank)
QAa1
QAa2
9
29
High
QAa3
QAa2
10
QAa3
11
Auto Precharge
12
Write with
(B-Bank)
DBb0
DBb0
CBb
13
DBb1
DBb1
AMIC Technology, Corp.
14
DBb2
DBb2
15
DBb3
DBb3
16
A43E16161
Auto Precharge
17
Start Point
(B-Bank)
: Don't care
18
19

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