A43E16161V AMIC Technology, Corp., A43E16161V Datasheet - Page 27

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A43E16161V

Manufacturer Part Number
A43E16161V
Description
1M x 16-Bit x 2 Banks Low Power Synchronous DRAM
Manufacturer
AMIC Technology, Corp.
Datasheet
Page Read Cycle at Different Bank @Burst Length = 4
PRELIMINARY
CLOCK
A10/AP
ADDR
(CL=2)
(CL=3)
CKE
RAS
CAS
DQM
DQ
DQ
CS
WE
BA
*Note 1
0
* Note : 1.
Row Active
(A-Bank)
RAa
RAa
1
2. To interrupt a burst read by row precharge, both the read ad the precharge banks must be the same.
(August, 2005, Version 0.0)
CS
2
can be don’t care when
3
(A-Bank)
Read
CAa
4
Row Active
(B-Bank)
RBb
RBb
5
QAa0 QAa1 QAa2 QAa3
6
RAS
QAa0 QAa1 QAa2 QAa3
,
7
CAS
(B-Bank)
Read
CBb
8
and
9
WE
26
High
QBb0
are high at the clock high going edge.
10
QBb1
QBb0
11
(A-Bank)
QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
QBb1
Read
CAc
12
QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
13
(B-Bank)
Read
CBd
AMIC Technology, Corp.
14
15
(A-Bank)
Read
CAe
16
A43E16161
17
Precharge
(A-Bank)
: Don't care
18
*Note 2
19

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