CS61582-IQ5R Cirrus Logic, Inc., CS61582-IQ5R Datasheet - Page 11

• Manufacturer Part Number: CS61582-IQ5R
• Description: Transmission/Switching, Dual T1/E1 Line Interface, Tape And Reel
• Manufacturer: Cirrus Logic, Inc.

The clock recovery circuit is a second-order
phase locked loop that can tolerate up to 0.4 UI
of jitter from 10 kHz to 100 kHz without gener-
ating errors (Figure 7). The clock and data
recovery circuit is tolerant of long strings of con-
secutive zeros and will successfully recover a
1-in-175 jitter-free line input signal.
P E A K -T O -P E A K
Recovered data at RPOS and RNEG is stable
and may be sampled using the recovered clock
RCLK. The CLKE input determines the clock
polarity where the output data is stable and valid
as shown in Table 2. When CLKE is low, RPOS
and RNEG are valid on the rising edge of
RCLK. When CLKE is high, RPOS and RNEG
are valid on the falling edge of RCLK.
JITTER ATTENUATOR
The jitter attenuator is located in the transmit
path of each channel to remove gapped clock jit-
ter on TCLK. Figure 8 illustrates the typical
jitter attenuation curve.
DS224PP1
(unit inte rvals)
Figure 7. Minimum Input Jitter Tolerance of Receiver
CLKE
JIT T E R
HIGH
LOW
Table 2. Recovered Data/Clock Options
300
138
100
28
10
.4
.1
1
1
RNEG
RNEG
RPOS
RPOS
DATA
(1990 V ersion)
A T& T 62411
1 0
JITT E R F R E Q U E N C Y (H z)
C S 61582
P erform ance
100
CLOCK
RCLK
RCLK
RCLK
RCLK
30 0
70 0
1k
for Valid Data
Clock Edge
Falling
Falling
Rising
Rising
1 0 k
100k
The attenuator consists of a 64-bit FIFO, a nar-
row-band monolithic PLL, and control logic.
Signal jitter is absorbed in the FIFO which is de-
signed to neither overflow nor underflow. If
overflow or underflow is imminent, the jitter
transfer function is altered to insure that no bit-
errors occur. Under this condition, jitter gain
may occur and jitter should be attenuated exter-
nally in a frame buffer. The jitter attenuator will
typically tolerate 43 UIs before the overflow/un-
d erflow mechanism occurs. If the jitter
attenuator has not had time to "lock" to the aver-
age incoming frequency (e.g., following a device
reset) the attenuator will tolerate a minimum of
22 UIs before the overflow/underflow mecha-
nism occurs. The attenuator can accept a
transmit clock with gaps
clock burst rate of
When a loss of signal occurs, the last recovered
frequency is not held and the output frequency be-
comes the frequency of the reference clock.
REFERENCE CLOCK
The CS61582 requires a reference clock with a
minimum accuracy of
applications. This clock can be either a 1X clock
(i.e., 1.544 MHz or 2.048 MHz), or can be a 8X
clock (i.e., 12.352 MHz or 16.384 MHz) as se-
1 0
2 0
3 0
4 0
5 0
6 0
0
1
Figure 8. Typical Jitter Transfer Function
b ) M a xim um
A tte n uatio n
Lim it
10
a) M in im u m A tte nua tion Lim it
Frequ ency in H z
10 0
8 MHz.
6 2411 (199 0 V ersion)
C S 61582 P e rform an ce
R e quirem ents
28 UIs and a transmit
ppm for T1 and E1
1 k
10 k
11