CS61582-IQ5R Cirrus Logic, Inc., CS61582-IQ5R Datasheet - Page 13

• Manufacturer Part Number: CS61582-IQ5R
• Description: Transmission/Switching, Dual T1/E1 Line Interface, Tape And Reel
• Manufacturer: Cirrus Logic, Inc.

Remote Loopback
A remote loopback is selected by setting the
RLOOP pin high. Selecting RLOOP causes the
data received from the line interface at RTIP and
RRING to be looped back through the jitter at-
tenuator and retransmitted on TTIP and TRING.
Data transmitted at TPOS and TNEG is ignored,
but data recovered from RTIP and RRING con-
tinues to be transmitted on RPOS and RNEG.
Remote loopback is functional if TCLK is ab-
sent. A TAOS request overrides the data
transmitted to the line interface during a remote
loopback. Note that simultaneous selection of lo-
cal and remote loopback modes is not valid.
Reset Pin
The CS61582 is continuously calibrated during
operation to insure the performance of the device
over power supply and temperature. This con-
tinuous calibration function eliminates the need
to reset the line interface during operation.
A device reset may be selected by setting the
RESET pin high for a minimum of 200 ns. The
reset function initiates on the falling edge of RE-
SET and requires less than 20 ms to complete.
The control logic is initialized and the transmit
DS224PP1
J-TMS
J-TCK
J-TDI
Figure 9. Block Diagram of JTAG Circuitry
Digital output pins
parallel latched
parallel latched
Boundary Scan Data Register
Controller
Instruction (shift) Register
Device ID Data Register
TAP
output
output
Bypass Data Register
Digital input pins
and receive circuitry is calibrated if REFCLK
and TCLK are present.
JTAG BOUNDARY SCAN
Board testing is supported through JTAG bound-
ary scan. Using boundary scan, the integrity of
the digital paths between devices on a circuit
board can be verified. This verification is sup-
ported by the ability to externally set the signals
on the digital output pins of the CS61582, and to
externally read the signals present on the input
pins of the CS61582. Additionally, the manufac-
turer ID, part number and revision of the
CS61582 can be read during board test using
JTAG boundary scan.
As shown in Figure 9, the JTAG hardware con-
sists of data and instruction registers plus a Test
Access Port (TAP) controller. Control of the TAP
is achieved through signals applied to the Test
Mode Select (J-TMS) and Test Clock ( J-TCK)
input pins. Data is shifted into the registers via
the Test Data Input (J-TDI) pin, and shifted out
of the registers via the Test Data Output (J-TDO)
pin. Both J-TDI and J-TDO are clocked at a rate
determined by J-TCK. The Instruction register
defines which data register is accessed in the
JTAG Block
MUX
J-TDO
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