CS61582-IQ5R Cirrus Logic, Inc., CS61582-IQ5R Datasheet - Page 9

• Manufacturer Part Number: CS61582-IQ5R
• Description: Transmission/Switching, Dual T1/E1 Line Interface, Tape And Reel
• Manufacturer: Cirrus Logic, Inc.

OVERVIEW
The CS61582 is a dual line interface optimized
for highly-integrated T1/E1 asynchronous or
synchronous multiplexer applications such as
SONET or SDH. One board design can support
all T1/E1 short-haul modes by only changing
component values in the receive and transmit
paths (if REFCLK and TCLK are externally tied
together).
All control of the device is achieved via external
pins, eliminating the need for microprocessor
support. The following pin control options are
available on a per channel basis: line length se-
lection, transmit all ones, local loopback, and
remote loopback.
The line driver generates waveforms compatible
with E1 (CCITT G.703), T1 short haul (DSX-1)
and T1 FCC Part 68 Option A (DS1). A single
transformer turns ratio is used for all waveform
types. The driver internally matches the imped-
ance of the load, providing excellent return loss
to insure superior T1/E1 pulse quality. An addi-
tional benefit of the internal impedance matching
is a 50 percent reduction in power consumption
compared to implementing return loss using ex-
ternal resistors that causes the transmitter to
drive the equivalent of two line loads.
DS224PP1
O
C
N
2
0
0
0
0
1
1
1
1
O
C
N
1
0
0
1
1
0
0
1
1
O
C
N
0
0
1
0
1
0
1
0
1
Transmit Pulse
244 ns (50%)
244 ns (50%)
324 ns (50%)
350 ns (54%)
350 ns (54%)
350 ns (54%)
350 ns (54%)
350 ns (54%)
Width at 50%
Amplitude
Transmit Pulse Shape
E1: square, 2.37 Volts into 75
E1: square, 3.00 Volts into 120
DS1: FCC Part 68 Option A (0 dB)
DSX-1: 0-133 ft. / or DS1 FCC Part 68 Option A with undershoot
DSX-1: 133-266 ft.
DSX-1: 266-399 ft.
DSX-1: 399-533 ft.
DSX-1: 533-655 ft.
Table 1. Configuration Selection
The line receiver contains all the necessary clock
and data recovery circuits.
The jitter attenuator meets AT&T 62411 require-
ments when using a 1X or 8X reference clock
supplied by either a crystal oscillator or external
reference at the REFCLK input pin.
TRANSMITTER
The transmitter accepts data from a T1 or E1
system and outputs pulses of appropriate shape
to the line. The transmit clock (TCLK) and
transmit data (TPOS and TNEG) are supplied
synchronously. Data is sampled on the falling
edge of the TCLK input.
The configuration pins CON[2:0] control trans-
mitted pulse shapes, transmitter source
impedance, and receiver slicing level as shown in
Table 1. Typical output pulses are shown in Figures
5 and 6. These pulse shapes are fully pre-defined
by circuitry in the CS61582, and are fully compli-
ant with appropriate standards when used with our
application guidelines in standard installations.
Both channels must be operated at the same line rate
(both T1 or both E1).
Note that the pulse width for Part 68 Option A
(324 ns) is narrower than the optimal pulse
width for DSX-1 (350 ns). The CS61582 auto-
Receiver
Slicing
Level
65%
65%
65%
65%
65%
65%
50%
50%
9