A45L9332AE-6 AMIC Technology, Corp., A45L9332AE-6 Datasheet - Page 11

• Manufacturer Part Number: A45L9332AE-6
• Description: 256K x 32 Bit x 2 Banks Synchronous Graphic RAM
• Manufacturer: AMIC Technology, Corp.

Simplified Truth Table
Register
Refresh
Bank Active
& Row Addr.
Read &
Column Addr. Auto Precharge Enable
Write &
Column Addr. Auto Precharge Enable
Block Write &
Column Addr. Auto Precharge Enable
Burst Stop
Precharge
Clock Suspend or
Active Power Down
Precharge Power Down Mode
DQM
No Operation Command
Note : 1. OP Code : Operand Code
PRELIMINARY
2. MRS can be issued only at both banks precharge state.
3. Auto refresh functions as same as CBR refresh of DRAM.
A0~A10 : Program keys. (@MRS)
Color register exists only one per DQi which both banks share.
So dose Mask Register.
Color or mask is loaded into chip through DQ pin.
SMRS can be issued only if DQ’s are idle.
A new command can be issued at the next clock of MRS/SMRS.
The automatical precharge without Row precharge command is meant by “Auto”.
Auto/Self refresh can be issued only at both precharge state.
Auto Precharge Disable
Auto Precharge Disable
Auto Precharge Disable
Bank Selection
Both Banks
Mode Register Set
Special Mode Register Set
Auto Refresh
Self
Refresh
Write Per Bite Disable
Write Per Bit Enable
Command
(October, 2001, Version 0.1)
Entry
Exit
Entry
Entry
Exit
Exit
CKEn-1 CKEn
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
X
H
H
X
X
X
X
X
X
H
H
X
L
L
L
CS
10
H
H
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS CAS
H
X
H
H
H
H
H
X
X
H
X
V
X
H
X
L
L
L
L
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
X
H
X
H
H
H
H
X
X
H
X
V
X
H
X
L
L
L
L
L
WE
H
H
H
H
H
H
H
X
X
X
X
V
X
X
L
L
L
L
L
DSF DQM A10
H
X
H
H
X
X
X
V
X
X
L
L
L
L
L
L
L
AMIC Technology, Inc.
A45L9332A Series
X
X
X
X
X
X
X
X
X
X
X
X
X
V
X
V
V
V
V
V
X
OP CODE
A9 A8~A0 Notes
Row Addr.
H
H
H
H
L
L
L
L
X
X
X
X
X
X
X
Column
Column
Column
Addr.
Addr. 4,5,6,9
Addr. 4,5,6,9
X
1,2,7
4,5,9
1,2
4,5
4,6
4,5
4,5
3
3
3
3
4
7
8